L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
43
•
•
•
•
9 System Memory
The phyCORE
‑
i.MX 6UL/ULL provides three types of on-board memory:
DDR3 SDRAM: 128 GB DDR3 SDRAM (up to 2 GB)
NAND Flash: 128 MB (up to 2 GB)
eMMC (optional): 4 GB
≤
The following sections detail each memory type used on the phyCORE
‑
i.MX 6UL/ULL.
1. The maximum memory size listed is as of the printing of this manual.
Please contact PHYTEC for more information about additional, or new module configurations available.
9.1 DDR3-SDRAM (U6)
The RAM memory of the phyCORE
‑
i.MX 6UL/ULL is comprised of one 16-bit wide DDR3-SDRAM chip (U6). The chip is
connected to the special DDR interface called Multi-Mode DDR Controller (MMDC) of the i.MX 6UL/ULL
microcontroller.
The DDR3 memory is accessible starting at address 0x8000 0000.
Typically the DDR3-SDRAM initialization is performed by a boot loader or operating system following a power-on
reset and must not be changed at a later point by any application code. When writing custom code independent of
an operating system or boot loader, the SDRAM must be initialized by accessing the appropriate SDRAM
configuration registers on the i.MX 6UL/ULL controller. Refer to the
i.MX 6UL/ULL Reference Manual
for accessing and
configuring these registers.
9.2 NAND Flash Memory (U7)
Use of Flash as non-volatile memory on the phyCORE
‑
i.MX 6UL/ULL provides an easily reprogrammable means of
code storage.
The NAND Flash memory at U7 is connected to the General Purpose Media Interface (GPMI).
The Flash devices are programmable with 3.3 V. No dedicated programming voltage is required.
As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100,000 erase/
program cycles and a data retention rate of 10 years.
Any parts that are footprint (VFBGA-N63) and functionally compatible may be used with the phyCORE-i.MX 6UL/ULL.
9.3 I
2
C EEPROM (U3)
The phyCORE
‑
i.MX 6UL/ULL is populated with a non-volatile 4 kB I
2
EEPROM at U3. This memory can be used to
store configuration data or other general-purpose data. This device is accessed through I
2
C port 1 on the i.MX 6UL/
ULL. The control registers for I
2
C port 1 are mapped between addresses 0x021A 0000 and 0x021A 3FFF. Please see
the
i.MX 6UL/ULL Reference
Manual
for detailed information on the registers.
One solder jumper J10 is provided to configure chip enable signal E1 which allows changing the address for the
memory area, as well as for the additional ID page. Refer to
Configuring Chip Enable Signal E1 (J10)
for details on
setting this jumper.