Circuit Descriptions
7.
7.
Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Architecture
7.3 T-CON Architecture
Notes:
•
Only
new
circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.
7.1
Introduction
The TPM4.1E LA chassis is using the MT8222 for main
processing.
7.1.1
Implementation
A key component of this chassis is the TCON TL2428MC
7.1.2
TPM4.1E LA Architecture Overview
•
For details about the chassis diagrams refer to
chapter 10. Circuit Diagrams and PWB Layouts.
An overview of the TPM4.1E LA architecture can be found
in
Figure 7-1 Architecture of TPM4.1E LA
1
88
70_210_100
3
0
8
.ep
s
100
3
0
8
MM T
u
ner
74HC4052D
MUX
TV_CVB
S
Y,P
b
,Pr 1
CVB
S
1P
CVB
S3
P
S
IF_P
AUDR, AUDL
DDR
S
PI Fl
as
h
ROM / 4M
24C02
D
S
UB EDID
24C
3
2
NVRAM
I2C
C
S
4
33
4
DAC
S
PI
UART1
Cloning
(iTV-1)
(5P)
Video I/F
(iTV-2)
Y,P
b
,Pr 2
RP,GP,BP
24C02
DVI EDID
Rem
a
rk : Re
s
erve only for iTV f
u
nction
WT670
3
S
TDBY MCU
A
u
dio o
u
t(AR2, AL2)
A
u
dio In
Monitor O
u
t
TV OUT
A
u
dio o
u
t(AR
3
, AL
3
)
CVB
S
o
u
t
I2C
A
u
dio In
CVB
S
_
S
C0
Tcon
TL242
8
MC
S
ide
S
-Video
PC A
u
dio
YP
b
Pr 1 A
u
dio
YP
b
Pr 2
AV A
u
dio
MT
8
222
TTL/LVD
S
LCD
P
a
nel
Com P
a
ir
10P
(
3
P)
(7P)
IR Bo
a
rd
Key Bo
a
rd
2 × (2P)
L-R
S
pe
a
ker
LIP
S
/P
S
control
S
ide AV
YP
b
Pr 2 A
u
dio
HP
D-
S
UB
HDMI 1
HDMI 2
S
ide AV A
u
dio
MAX972
8
YP
b
Pr 1
AV IN
MAX972
8
MAX972
8
TPA
3
110D
S
CART 1
S
ide U
S
B
AR1,AL1
S
CART 2
CVB
S
2P
(CVB
S
0P)