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Philips Semiconductors

Product specification

SA7016

1.3GHz low voltage fractional-N synthesizer

1999 Nov 04

9

Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)

The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R

SET

in conjunction with bits CP0,

CP1 in the B-word (see table of charge pump ratios). The fractional
compensation is derived from the current at R

SET

, the contents of

the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.

Principle of Fractional Compensation

The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I

COMP

is the

compensation current and I

PUMP

is the pump current, then for each

charge pump:

I

PUMP_TOTAL

= I

PUMP

+ I

COMP

.

The compensation is done by sourcing a small current, I

COMP

, see

Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R

SET

, programming or speed-up operation.

For a given charge pump,

I

COMP

= ( I

PUMP

/ 128 ) * ( FDAC / 5*128) * FRD

FRD is the fractional accumulator value.

The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and
80 for FMOD = 0 (modulo 8).

SR01416

REFERENCE R

MAIN M
DIVIDE RATIO

DETECTOR
OUTPUT

ACCUMULATOR

FRACTIONAL
COMPENSATION
CURRENT

OUTPUT ON
PUMP

N

N

N+1

N

N+1

2

4

1

3

0

PULSE
WIDTH
MODULATION

PULSE LEVEL
MODULATION

mA

µ

A

NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.

Figure 6.

Waveforms for NF = 2 Modulo 5

→

fraction =

2

/

5

SR01682

f

RF

1930.140 MHz

MAIN DIVIDER

N = 8042

FRACTIONAL

ACCUMULATOR

f

REF

240 kHz

240.016 kHz

I

COMP

I

PUMP

LOOP FILTER

& VCO

FMOD

NF

Figure 7.

Current Injection Concept

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Содержание SA7016

Страница 1: ... SA7016 1 3GHz low voltage fractional N synthesizer Product specification Supersedes data of 1999 Apr 20 1999 Nov 04 INTEGRATED CIRCUITS ...

Страница 2: ...lters could be used the charge pump operates within a wide voltage compliance range to provide a wider tuning range FEATURES Low phase noise Low power Fully programmable main divider Internal fractional spurious compensation Hardware and software power down Split supply for VDD and VDDCP SR01505 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LOCK TEST VDD GND RFin RFin GNDCP PHP PON STROBE DATA CLOCK REFi...

Страница 3: ...9 8 1 PON 16 Figure 2 Block Diagram PINNING SYMBOL PIN DESCRIPTION LOCK 1 Lock detect output TEST 2 Test should be either grounded or connected to VDD VDD 3 Digital supply GND 4 Digital ground RFin 5 RF input to main divider RFin 6 RF input to main divider GNDCP 7 Charge pump ground PHP 8 Main normal chargepump VDDCP 9 Charge pump supply voltage RSET 10 External resistor from this pin to ground se...

Страница 4: ... to 16 0 3 VDD 0 3 V V1 Voltage at pin 8 9 0 3 VDDCP 0 3 V VGND Difference in voltage between GNDCP and GND these pins should be connected together 0 3 0 3 V Tstg Storage temperature 55 125 _C Tamb Operating ambient temperature 40 85 _C Tj Maximum junction temperature 150 _C Handling Inputs and outputs are protected against electrostatic discharge in normal handling However to be totally safe it i...

Страница 5: ...Hz 1 0 pF Nmain Main divider ratio 512 65535 fPCmax Maximum loop comparison frequency indicative not tested 4 MHz Reference divider input pins 11 12 fREFin Input frequency range from TCXO 5 40 MHz VRFin AC coupled input signal level single ended drive max limit is indicative 360 1300 mVPP ZREFin Input impedance real part fREF 20 MHz 10 kΩ CREFin Typical pin input capacitance fREF 20 MHz 1 0 pF RRE...

Страница 6: ... fCOMP 240kHz indicative not tested 85 dBc Hz Interface logic input signal levels pins 13 14 15 16 VIH HIGH level input voltage 0 7 VDD VDD 0 3 V VIL LOW level input voltage 0 3 0 3 VDD V ILEAK Input leakage current logic 1 or logic 0 0 5 0 5 µA Lock detect output signal in push pull mode pin 1 VOL LOW level output voltage Isink 2mA 0 4 V VOH HIGH level output voltage Isource 2mA VDD 0 4 V NOTES 1...

Страница 7: ...The output of the main divider will be modulated with a fractional phase ripple The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance Reference divider The reference divider consists of ...

Страница 8: ...6 1 3GHz low voltage fractional N synthesizer 1999 Nov 04 8 SR02103 R X P N REF DIVIDER AUX MAIN DIVIDER D Q CLK 1 R D R CLK 1 X Q N P τ VCC IPH GND P TYPE CHARGE PUMP N TYPE CHARGE PUMP R fREF fREF IPH τ τ Figure 5 Phase Detector Structure with Timing ...

Страница 9: ...ng a small current ICOMP see Figure 7 that is proportional to the fractional error phase For proper fractional compensation the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple The width of the fractional compensation pulse is fixed to 128 VCO cycles the amplitude is proportional to the fractional accumulator value and is adjusted by ...

Страница 10: ...n and auxiliary synthesizers is defined as a phase difference of less than 1 period of the frequency at the input REFin One counter can fulfill the lock condition when the other counter is powered down Out of lock logic 0 is indicated when both counters are powered down Power down mode The power down signal can be either hardware PON or software PD The PON signal is exclusively ORed with the PD bi...

Страница 11: ...The D word is normally used for testing purposes When sending the B word data bits FC7 0 for the fractional compensation DAC are not loaded immediately Instead they are stored in temporary registers Only when the A word is loaded these temporary registers are loaded together with the main divider ratio Serial bus timing characteristics See Figure 8 VDD VDDCP 3 0V Tamb 25 C unless otherwise specifi...

Страница 12: ...1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LO MAIN CP0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 SP3 Default 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 B word select Fixed to 01 R Divider R0 R9 Reference divider values 4 to 1023 allowed for divider ration Charge pump current Ratio CP0 Charge pump current ratio see table of charge pump currents Lock detect output L0 0 Main lock detect signal present at the LOCK pin pu...

Страница 13: ...AGE V ISET 206 67 mA ISET 165 33 mA ISET 103 33 mA ISET 51 67 mA ISET 51 67 mA ISET 103 33 mA ISET 165 33 mA ISET 206 67 mA Figure 11 Php Charge Pump Output vs ISET CP 1 TEMP 25_C SR01914 200 Icp uA 200 150 100 50 0 50 100 150 0 0 25 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 2 75 3 3 25 3 5 COMPLIANCE VOLTAGE V TEMP 85 C TEMP 25 C TEMP 40 C Vdd 3 0 V ISET 165 33 µA Figure 12 Php Charge Pump Output vs Te...

Страница 14: ... V VDD 2 70 V 35 30 25 20 15 10 5 0 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY MHz 45 50 55 60 1800 2000 Figure 17 Main Divider Input Sensitivity vs Frequency and Supply Voltage TEMP 25_C SR01930 45 MINIMUM SIGNAL INPUT LEVEL dBm 85_C 25_C 40_C 40 35 30 25 20 15 10 0 5 0 200 400 600 800 1000 1200 1400 1600 1800 FREQUENCY MHz 50 2000 Figure 18 Main Divider Input Sensitivity vs Frequency and Te...

Страница 15: ...uct specification SA7016 1 3GHz low voltage fractional N synthesizer 1999 Nov 04 15 SR01931 8 I TOTAL mA 8 5 7 5 7 6 5 6 5 5 2 5 3 3 5 4 4 5 5 5 5 6 TEMP 85_C TEMP 25_C TEMP 40_C SUPPLY VOLTAGE V Figure 21 Current Supply Over VDD ...

Страница 16: ...3GHz low voltage fractional N frequency synthesizer Philips Semiconductors Product specification SA7016 1999 Nov 04 16 TSSOP16 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 ...

Страница 17: ...1 3GHz low voltage fractional N frequency synthesizer Philips Semiconductors Product specification SA7016 1999 Nov 04 17 NOTES ...

Страница 18: ...on Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mas...

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