Block Diagrams, Test Point Overview, and Waveforms
EN 57
SDI PDP 2K6
6.
6.2
Block Diagram for Logic Circuit
Figure 6-3 Block diagram (42" SD v5)
Figure 6-4 Block diagram (42" HD w1)
Figure 6-5 Block diagram (50" HD w1 and 63” HD v4)
ASIC
SPS -S101
128K
DDR
128K
DDR
L VD S
IN PU T
( C L OC K
R,G,B D ata
V, H Sync.
D E)
I2 C
In te rfa c e
Si g n a l
X, Y
FET
C o n tro l
TC P
C L K, D ATA
C o n tro l
Lo g ic M ain Blo ck D iag ram
ASIC
SPS -S101
128 M
DDR
128M
DDR
L VD S
IN PU T
( C L OC K
R,G,B D ata
V, H Sync.
D E)
I2 C
In te rfa c e
Si g n a l
X, Y
FET
C o n tro l
TC P
C L K, D ATA
C o n tro l
Lo g ic M ain Blo ck D iag ram
G_16380_222.eps
190606
FET
Logic Main Block Diagram
SPS-H102
Interface
Signal
UART
LVDS
ASIC
Input
(Clock
RGB data
V-H-sync.
DE)
X-Y
DDR
128M
DDR
128M
CLK, DATA
TCP
Control
Control
G_16380_223.eps
190606
FET
Logic Main Block Diagram
SPS-H102
Interface
Signal
I2C
LVDS
ASIC
Input
(Clock
RGB data
V-H-sync.
DE)
X-Y
DDR
128M
DDR
128M
CLK, DATA
TCP
Control
Control
G_16380_224.eps
190606