Circuit Diagrams and PWB Layouts
10.
Main Board: Low Power Monitor
5
4
3
2
1
D
C
B
A
A
XTAL
TCLK
OBUFC_CLK
+3.3V_LPM_S
+1.2V_LPM_S
+3.3V_I/O
+3.3V_LPM
+1.2V_LPM
RX_LPM
TX_LPM
+5VS
UDI_LPM
IR0
UDO_LPM
CEC_LPM
TXP
TXP
RXP
RXP
HW_RESET
HA_CEC
HA_CEC
IR_LPM
21
RX_LPM
8
TX_LPM
8
+3.3V_I/O 5,6,16,17,19
+3.3V_LPM 19,20
+1.2V_LPM 20
+5VS
2,3,7,17,18,19,20,21,22
PWRKEY_LPM
21
SYSTEM_RESET
RXP
TXP
SYS_POWERON
17,19,21,22
HA_CEC 2
CEC_POWERON
21
+1.2V_LPM
+3.3V_LPM
+3.3V_LPM
+3.3V_LPM
+3.3V_LPM
+1.2V_LPM
+3.3V_I/O
+5VS
+5VS
+3.3V_LPM
+5VS
+5VS
Title
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WLZSA1 ST FLI32626
D2A
Low Power Monitor
PROJECT NAME:
WLZR-A1
A4
15
22
Thursday, January 08, 2009
1
0
0
FUNCTION
1
0
TEST_
EN1
Regular mission mode with POR delayed output tied to internal Resetn
JTAG boundary scan enable. 5-additional pins become enabled for JTAG
1
Regular mission mode with POR non-delayed output tied to internal
RESETn (For ATE vectors)
SCAN is enabled here and ALTERNATE(TBD) pad is used as internal RESETn substitute
1
0
TEST_
EN0
C243
0.1uF/6
R677
0R/6/NC
+
C242
22uF/6.3V
1
2
C239
0.1uF/6
R3
3
0
100R/6
C244
1nF/6
R334
10K/6/NC
R343
10K/6/NC
R336
10K/6/NC
C246
0.1uF/6
SEQUOIA Low
Power Monitor
U8K
FLI32626H
CEC_LPM
Y1
IR_LPM
AA2
UDO_LPM
AB1
UDI_LPM
AC1
LPM_GPIO0
AA3
LPM_GPIO3
AA1
I/
O_VDD_33_LPM
Y3
CORE_12_LPM
Y4
D33
UDZ5V6B/NC
2
1
R638
0R/6
+
C237
22uF/6.3V
1
2
C245
1nF/6
R513
0R/6
R342
10K/6
C247
22pF/6
C238
0.1uF/6
R512 0R/6/NC
CN11
4500-E04N
1
2
3
4
R346
0R/6
L44
0R/8
C249
22pF/6/NC
R332
10K/6/NC
R710
0R/6/NC
R3
3
1
100R/6
Q41
MMBT3904
3
1
2
R341
0R/6
C250
22pF/6/NC
D34
UDZ5V6B/NC
2
1
R711
4.7K/6
X1
19.6608MHz
R335
10K/6/NC
R340
10K/6/NC
R333
0R/6
L43
0R/8
C248
22pF/6
R709
10K/6
+
C240
22uF/6.3V
1
2
TP3
+
C241
22uF/6.3V
1
2
SEQUOIA Test
U8G
FLI32626H
TEST_EN0
AB2
TEST_EN1
AC2
RESETn
AC7
R639
0R/6
TP4
SEQUOIA Internal
Clock Generation
U8L
FLI32626H
XTAL
AC4
TCLK
AC5
OBUF_C
AA4
RPLL_3.
3
AB5
MPLL_3.
3
AB3
RPLL_1.
2
AC3
MPLL_1.
2
AA5
RPLL_GND
AB4
MPLL_GND
Y5
R345
0R/6
1
8
4
3
0_51
3
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s
090202