background image

Philips Semiconductors

Product specification

PTN3501

Maintenance and control device

2

2001 Jan 17

853-2227 25436

FEATURES

I

2

C to parallel port expander

Internal 256x8 E

2

PROM

Self timed write cycle (5 ms typ.)

16 byte page write operation

Controlled pull-up on address lines

Low voltage V

CC

 range of +2.5 V to +3.6 V

5 V – tolerant I/Os

Low standby current (< 60 

µ

A )

Power on Reset

Supports Live Insertion

Compatible with SMBus specification version 1.1

High E

2

PROM endurance and data retention

Available in TSSOP20 package

DESCRIPTION

The PTN3501 is a general purpose maintenance and control device.
It features an on-board E

2

PROM that can be used to store error

codes or board manufacturing data for read–back by application
software for diagnostic purposes.

The eight quasi bidirectional data pins can be independently
assigned as inputs or outputs to monitor board level status or
activate indicator devices such as LEDs.

The PTN3501 has six address pins allowing up to 64 devices to
share the common two wire I

2

C software protocol serial data bus.

The PTN3501 supports live insertion to facilitate usage in removable
cards on backplane systems.

The PTN3501 is an alternative to the functionally similar PTN3500
for systems where a high number of devices are required to share
the same I

2

C-bus without need for an additional I

2

C-bus I/O

expander.

PIN CONFIGURATION

1

2

3

4

5

6

7

20

19

18

17

16

15

14

A0

A1

A2

P0

P1

P2

P3

SDA

SCL

P7

P6

P5

WC

V

DD

SW00657

PTN3501

8

13

P4

9

10

12

11

A5

A3

A4

V

SS

INT

Figure 1.  

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1,2,3,9,11,12

A0:5

Address Lines

4,5,6,7

P0:3

Quasi–bidirectional I/O pins

10

V

SS

Ground

13,14,15,16

P4:7

Quasi–bidirectional I/O pins

17

WC

Write Control Pin. Should be
tied LOW.

8

INT

Interrupt Pin

18

SCL

I

2

C Serial Clock

19

SDA

I

2

C Serial Data

20

V

DD

Supply Voltage

ORDERING INFORMATION

Type n mber

Package

Type number

Name

Description

Version

PTN3501DH

TSSOP20

Plastic thin shrink small-outline package; 20 leads; body width 4.4 mm

SOT360-1

FUNCTIONAL DIAGRAM

I

2

C

CONTROL

8-BIT

I/O PORT

P7:0

A5:0

SDA

SCL

E2PROM

256 

×

 8

WC

INT

SW00647

Figure 2.  

Содержание PTN3501

Страница 1: ... PTN3501 Maintenance and control device Product specification Supersedes data of 2000 Nov 22 2001 Jan 17 INTEGRATED CIRCUITS ...

Страница 2: ...s allowing up to 64 devices to share the common two wire I2C software protocol serial data bus The PTN3501 supports live insertion to facilitate usage in removable cards on backplane systems The PTN3501 is an alternative to the functionally similar PTN3500 for systems where a high number of devices are required to share the same I2C bus without need for an additional I2C bus I O expander PIN CONFI...

Страница 3: ...e 3 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the start condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the stop condition P see Figure 4 System configuration A device generating a message is a transmitter a device receiving is t...

Страница 4: ... to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be taken into account A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leav...

Страница 5: ... as an input or output Input I O data is transferred from the port to the microcontroller by the READ mode See Figure 10 Output data is transmitted to the port by the I O WRITE mode see Figure 9 S 0 A5 A4 A3 A2 A1 A0 0 A DATA 1 A DATA 2 A SDA SCL tpv 1 2 3 4 5 6 7 8 tpv DATA 2 VALID DATA 1 VALID SW00649 ACKNOWLEDGE FROM SLAVE R W START CONDITION ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE SLAVE ...

Страница 6: ...ignal In the WRITE mode at the acknowledge bit after the HIGH to LOW transition of the SCL signal Returning of the port data to its original setting A second port state change will require an SCL rising clock edge to be captured as an INT event Interrupts which occur during the acknowledge clock pulse may be lost or very short due to the resetting of the interrupt during this pulse Each change of ...

Страница 7: ... and are switched off by the negative edge of SCL The I Os should be HIGH before being used as inputs S 0 A2 A1 A0 0 A A A SDA SCL 1 2 3 4 5 6 7 8 SW00789 ACKNOWLEDGE FROM SLAVE R W START CONDITION ACKNOWLEDGE FROM SLAVE SLAVE ADDRESS PTN3501 DATA TO PORT DATA TO PORT 1 P3 0 P3 P P3 OUTPUT VOLTAGE P3 PULL UP OUTPUT CURRENT IOHt IOH A5 A4 A3 Figure 13 Transient pull up current IOHt while P3 changes...

Страница 8: ...he quasi bidirectional I Os are allowed during the internal write cycle Page Write see Figure 15 A page write is initiated in the same way as the byte write if after sending the first word of data the stop condition is not received the PTN3501 considers subsequent words as data After each data word the PTN3501 responds with an acknowledge and the four least significant bits of the memory address f...

Страница 9: ...and use the next eight clock cycles to transmit the data contained in the addressed location The master ceases the transmission by issuing the stop condition after the eighth bit omitting the ninth clock cycle acknowledge Sequential Read see Figure 18 The PTN3501 sequential read is an extension of either the current address read or random read If the master doesn t issue a stop condition after it ...

Страница 10: ... MAX UNIT Supply VDD Supply Voltage 2 5 3 3 3 6 V IDDQ Standby Current A0 thru A5 WC HIGH 60 µA IDD1 Supply Current Read 1 mA IDD2 Supply Current Write 2 mA VPOR Power on Reset Voltage 2 4 V Input SCL input output SDA VIL Input LOW voltage 0 5 0 3 VDD V VIH Input HIGH voltage 0 7 VDD 5 5 V IOL Output LOW current VOL 0 4 V 3 mA IL Input leakage current VI VDD or VSS 1 1 µA CI Input capacitance VI V...

Страница 11: ...SDA rise time 0 3 µs tf SCL and SDA fall time 0 3 µs tSU DAT data set up time 250 ns tHD DAT data hold time 0 ns tVD DAT SCL LOW to data out valid 1 0 µs tSU STO STOP condition set up time 0 6 µs NOTE 1 All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD handbook full pagewidth SCL SDA ...

Страница 12: ...UW are the delays required from the time VCC is stable until the specified operation can be initiated These parameters are guaranteed by design WRITE CYCLE LIMITS SYMBOL PARAMETER MIN TYP 5 MAX UNIT tWR 1 Write Cycle Time 5 10 ms NOTE 1 tWR is the maximum time that the device requires to perform the internal write operation Write Cycle Timing SCL SDA 8th Bit Word n ACK Stop Condition Start Conditi...

Страница 13: ...conduction by heated belt Dwell times vary between 50 and 300 seconds depending on heating method Typical reflow temperatures range from 215 to 250 C Preheating is necessary to dry the paste and evaporate the binding agent Preheating duration 45 minutes at 45 C Wave soldering Wave soldering is not recommended for SSOP packages This is because of the likelihood of solder bridging due to closely spa...

Страница 14: ...Philips Semiconductors Product specification PTN3501 Maintenance and control device 2001 Jan 17 14 TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1 ...

Страница 15: ...make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right...

Отзывы: