© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 03 — 7 June 2005
22 of 139
Philips Semiconductors
UM10119
P89LPC938 User manual
2.7 Oscillator Clock (OSCCLK) wake-up delay
The P89LPC938 has an internal wake-up timer that delays the clock until it stabilizes
depending to the clock source used. If the clock source is any of the three crystal
selections, the delay is 992 OSCCLK cycles plus 60
µ
s to 100
µ
s. If the clock source is
either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK
cycles plus 60
µ
s to 100
µ
s.
2.8 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down, by an integer, up to 510 times by
configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK
frequency using the following formula:
CCLK frequency = f
osc
/ (2N)
Where: f
osc
is the frequency of OSCCLK, N is the value of DIVM.
Since N ranges from 0 to 255, the CCLK frequency can be in the range of f
osc
to f
osc
/510.
(for N = 0, CCLK = f
osc
).
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power
consumption. By dividing the clock, the CPU can retain the ability to respond to events
other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by
executing its normal program at a lower rate. This can often result in lower power
consumption than in Idle mode. This can allow bypassing the oscillator start-up time in
cases where Power-down mode would otherwise be used. The value of DIVM may be
changed by the program at any time without interrupting code execution.
2.9 Low power select
The P89LPC938 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This
bit can then be set in software if CCLK is running at 8 MHz or slower.
3.
A/D converter
3.1 General description
The P89LPC938 has a 10-bit, 8-channel multiplexed successive approximation
analog-to-digital converter module. A block diagram of the A/D converter is shown in
. The A/D consists of an 8-input multiplexer which feeds a sample-and-hold circuit
providing an input signal to one of two comparator inputs. The control logic in combination
with the SAR drives a digital-to-analog converter which provides the other input to the
comparator. The output of the comparator is fed to the SAR.
3.2 A/D features
•
10-bit, 8-channel multiplexed input, successive approximation A/D converter.
•
Eight result register pairs.
•
Six operating modes
