Philips Semiconductors
User’s Manual - Preliminary -
P89LPC901/902/903
WATCHDOG TIMER
2003 Dec 8
88
Note:
When switching clocks, it is important that the old clock source is left enabled for 2 clock cycles after the feed completes.
Otherwise, the watchdog may become disabled when the old clock source is disabled. For example, suppose PCLK (WCLK=0)
is the current clock source. After WCLK is set to ’1’, the program should wait at least two PCLK cycles (4 CCLKs) after the feed
completes before going into Power down mode. Otherwise, the watchdog could become disabled when CCLK turns off. The
watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first.
Содержание P89LPC901
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