Philips MX5500D/21S, Руководство по обслуживанию

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Pin Name Pin No. Type Description
Host Interface Pins
XHCS1J 94 I This pin is used to select the command block task file registers.
XHCS3J 93 I This pin is used to select the control block task file registers.
XHIORJ 103 I Asserted by the host during a host I/O read operation.
XHIOWJ 104 I Asserted by the host during a host I/O write operation.
XHDRQ 105 O 1. DMA request . This pin is configured as the DMA request signal, and is
used during DMA transfer between the host and the controller. This pin is
tri-stated when DMA transfers are not enabled.
2. MPEG acknowledge . This pin is us ed as the ACKJ signal when MPEG
interface mode is selected.
XHDACKJ 101 I 1. DMA acknowledge . This pin is configured as DACKJ, and is used as the
DMA acknowledge signal during DMA data transfers.
2. MPEG request . This pin is us ed as the REQ signal when MPEG interface
mode is selected.
XHCS16J 99 O 1. 16-bit data select . This signal indicates that a 16-bit data transfer is active
on the host data bus. This pin is open-drain tri-state output.
2. MPEG clock . This pin is us ed as the CLOCK signal when MPEG interface
mode is selected.
XHRSTJ 50 I Host Reset. The reset of ATA bus
XHINT 100 O 1. Host interrupt request . This tri-state pin is the host interrupt request, and
is asserted to indicate to the host that the controller needs attention.
2. MPEG begin . This pin is us ed as the BEGIN signal when MPEG interface
mode is selected.
XHPDIAGJ 97 I/O This pin is used as the Passed Diagnostics signal, and may be an input or an
open-drain output.
XHDASPJ 92 I/O This pin is used as the Drive Active/ Slave Present signal, and is an input or an
open-drain output. This pin is used for Master/Slave drive communication
and/or for driving an LED.
XHIORDY 102 O 1. I/O channel ready . This signal is driven low to extend host transfer cycles
when the controller is not ready to respond. This pin will be tri-stated when a
read or write is not in progress.
2. MPEG error . This pin is us ed as the ERROR signal when MPEG interface
mode is selected.
XHA[2:0] 95, 98, 96 I Host address lines . The host address lines A[2:0] are used to access the
various host control, status, and data registers.
XHD[15:0] 106, 108,
111, 113,
116, 118,
120, 122,
123, 121,
119, 117,
114, 112,
109, 107
I/O 1. Host data bus . This bus is used to transfer data and status between the
host and the controller.
2. MPEG data bus 7-0 . The HD[7:0] are us ed as the DATA[7:0] when MPEG
interface mode is selected.
3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled.
The relationship of bit3 -0 and VCD I/F is as follow.
HD0
CD-DATA
HD1 CD-LRCK
HD2 CD-BCK
HD3 CD-C2PO
Pin Name Pin No. Type Description
RAM Interface Pins
XRSDCLK 143 O This signal is the clock output for SDRAM.
XROEJ 147 O This signal is used as the memory output enable for external DRAM buffers.
After RSTJ is asserted, this signal will be low.
XRWEJ 142 O This signal is asserted low when a buffer memory write operation is active.
XRRASJ 144 O This signal is used as Row address output to external DRAM buffer. After
RSTJ is asserted, this signal will be high.
XRCASJ 145 O This signal is used as column address output to external DRAM. After RSTJ is
asserted, this signal will be high.
XRA[11:0] 151, 152,
148, 149,
153, 155,
156, 157,
161, 160,
159, 158 O 1. RAM address lines . These are bits 11-0 for addressing the buffer memory.
2. Hardware setting . The bits 6-0 are used as hardware setting for some
functions.
RA[9] : FLASH size is 64K/128K
1 : FLASH size is 64K.
0 : FLASH size is 128K.
RA[8] : External CPU is 8032/H8
1 : 8032
0 : H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1 : By internal microcontroller.
0 : By registers to decide input/output.
RA[6] : System testpin output.
1 : Normal operation.
0 : System test pin output.
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave.
1 : Slave.
0 : Master.
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection.
11 : Normal Mode (internal uP,internal address latch).
10 : Outside uP Mode (ICE Mode).
01 : Test mode for internal uP testing.
00 : Internal uP mode with external address latch.
XRD[15:0] 124, 126,
128, 131,
133, 135,
137, 140,
141, 139,
136, 134,
132, 129,
127, 125
I/O These signals are the 8 -bit parallel data lines to/from the buffer memory.
M5705 Pins Descriptions