Philips MC-M350 SERIES, Руководство по обслуживанию

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ES3210 PINOUT
ES3210 PIN DESCRIPTION
1
VSS
AUX4
AUX3
AUX2
AUX1
AUX0
PCLK
PCLK2X
CPUCLK
HSYNC
VSYNC
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
VDD
VPP
LA12
LA13
LA14
LA15
LA16
LA17
ACLK
AOUT/SEL_PLL0
ATCLK
ATFS/SEL_PLL1
DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
DBUS8 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0
MA
8
MA
7
MA
6
MA
5
MA
4
MA
3
MA
2
MA
1
MA
0
RAS#
VDD
VS
S
RESET#
DWE#
DBUS14 DBUS15 DBUS1
3
DBUS1
2
DB
U
S
1
1
DBUS1
0
DBUS9
LD6 LD
7
LW
R
#
LO
E
#
LCS3# LC
S
1
#
LC
S
0
#
LA0 LA
1
LA2 LA
3
LA
4
LA5 LA
6
LA
7
LA8 LA
9
LA10 LA
1
1
VSS VDD AUX6 AUX5 AUX7 LD
0
LD1 LD2 LD3 LD
4
LD
5
31
30
51
50
80
81
100
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ES3210
100-pin PQFP
Name Number I/O Definition
VDD 1, 31, 51 I Voltage supply for 3.3V.
RAS# 2 O DRAM row address strobe (active low).
DWE# 3 O DRAM write enable (active low).
MA[8:0] 12:4 O DRAM multiplexed row and column address bus.
DBUS[15:0] 28:13 I/O DRAM data bus I/O [15:0].
RESET# 29 I System reset (active low).
VSS 30, 50, 80, 100 I Ground.
YUV[7:0] 39:32 O YUV[7:0] pixel output data.
VSYNC 40 I/O Vertical sync for screen video interface, programmable for rising or falling edge.
HSYNC 41 I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
CPUCLK 42 I RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00.
PCLK2X 43 I/O Pixel clock; two times the actual pixel clock for screen video interface.
PCLK 44 I/O Pixel clock qualifier in for screen video interface.
AUX[7:0] 54:52, 49:45 I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
LD[7:0] 62:55 I/O RISC interface data bus.
LWR# 63 O RISC interface write enable (active low).
LOE# 64 O RISC interface output enable (active low).
LCS[3,1,0]# 65:67 O RISC interface chip select (active low).
LA[17:0] 87:82, 79:68 O RISC interface address bus.
VPP 81 I Digital supply voltage for 5V.
ACLK 88 I/O Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz).
AOUT/ 89 O Dual-purpose pin. AOUT is the audio interface serial data output
SEL_PLL0 I Select PLL[0] input. The matrix below lists the available clock frequencies and their
respective PLL bit settings.
ATCLK 90 I/O Audio transmit bit clock.
ATFS 91 O Audio transmit frame sync.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL0 pin 89.
DOE# 92 O DRAM output enable (active low).
AIN 93 I Audio serial data input.
ARCLK 94 I Audio receive bit clock.
ARFS 95 I Audio receive frame sync.
TDMCLK 96 I TDM interface serial clock.
TDMDR 97 I TDM interface serial data receive.
TDMFS 98 I TDM interface frame sync.
CAS# 99 O DRAM column address strobe bank 0 (active low).
Name Number I/O Definition
SEL_PLL1 SEL_PLL0 Clock Output
0 0 Bypass PLL
0 1 54.0 MHz
1 0 67.5 MHz
1 1 81.0 MHz
PIN DESCRIPTION (Continued)
VIDEO CD PROCESSOR
ES3210 VIDEO CD PROCESSOR
ES3210
8-5
8-5