Circuit-, IC descriptions and list of abbreviations
EN 168
9.
2001 Aug 01
7
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SAA6752HS
6
PINNING
SYMBOL
PIN
INPUT/OUTPUT
(1)
I
max
(mA)
DESCRIPTION
V
SSP
1
ground
−
pad ground
SDATA1
2
input
−
I
2
S-bus serial data input port 1 with internal pull-down resistor
SCLK1
3
input/output
4
I
2
S-bus serial clock port 1 with internal pull-down resistor
SWS1
4
input/output
4
I
2
S-bus word select port 1 with internal pull-down resistor
V
DDP
5
supply
−
pad ring supply voltage (3.3 V)
SDATA2
6
input/output
4
I
2
S-bus serial data port 2 with internal pull-down resistor
SCLK2
7
input/output
4
I
2
S-bus serial clock port 2 with internal pull-down resistor
SWS2
8
input/output
4
I
2
S-bus word select port 2 with internal pull-down resistor
ACLK
9
output
4
audio clock output (256
×
f
s
or 384
×
f
s
)
V
SSP
10
ground
−
pad ground
IDQ
11
input
−
reserved (recommended connect to pin V
SSP
) with internal
pull-down resistor
YUV0
12
input
−
video input signal bit 0 (LSB)
YUV1
13
input
−
video input signal bit 1
YUV2
14
input
−
video input signal bit 2
YUV3
15
input
−
video input signal bit 3
YUV4
16
input
−
video input signal bit 4
YUV5
17
input
−
video input signal bit 5
YUV6
18
input
−
video input signal bit 6
YUV7
19
input
−
video input signal bit 7 (MSB)
V
SSP
20
ground
−
pad ground
HSYNC
21
input
−
horizontal sync input (video) with internal pull-down resistor
VSYNC
22
input
−
vertical sync input (video) with internal pull-down resistor
FID
23
input
−
video ?eld identi?cation input (odd/even ?eld) with internal
pull-down resistor
VCLK1
24
input
−
video clock input 1 (27 MHz) with internal pull-down resistor
V
SSCO
25
ground
−
core ground
V
SSCO
26
ground
−
core ground
V
DDCO
27
supply
−
core supply voltage (2.5 V)
V
DDCO
28
supply
−
core supply voltage (2.5 V)
V
DDP
29
supply
−
pad ring supply voltage (3.3 V)
VCLK2
30
input
−
video clock input 2 (27 MHz) with internal pull-down resistor
PDOAV
31
3-state output
4
parallel stream data output for audio/video identi?er
PDIDS
32
input
−
parallel stream data input for data strobe (request for packet in
Data Expansion Bus Interface (DEBI) slave mode) with internal
pull-up resistor
PDOSYNC
33
3-state output
4
parallel stream data output for packet sync
V
SSP
34
ground
−
pad ground
PDOVAL
35
3-state output
4
parallel stream data valid output with internal pull-up resistor
PDO0
36
3-state output
4
parallel stream data output bit 0 (LSB)
Содержание LX9000R/22
Страница 58: ...Diagnostic Software DVD EN 58 LX9000R 5 ...
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Страница 108: ...EN 108 7 LX9000R Circuit Diagrams and PWB Layouts DVIO BOARD top view ...
Страница 109: ...EN 109 7 LX9000R Circuit Diagrams and PWB Layouts DVIO BOARD top view ...
Страница 110: ...EN 110 7 LX9000R Circuit Diagrams and PWB Layouts DVIO BOARD top view ...
Страница 111: ...EN 111 7 LX9000R Circuit Diagrams and PWB Layouts TEST POINTS OVERVIEW DVIO BOARD ...
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Страница 123: ...EN 123 7 LX9000R Circuit Diagrams and PWB Layouts DIGITAL BOARD 1 5 top view TR 06014b_001 120203 ...
Страница 125: ...EN 125 7 LX9000R Circuit Diagrams and PWB Layouts TR 06015a_001 250203 DIGITAL BOARD 1 5 bottom view ...
Страница 126: ...EN 126 7 LX9000R Circuit Diagrams and PWB Layouts TR 06015b_001 180203 DIGITAL BOARD 1 5 bottom view ...
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