34
LC9_3L
7.6
I
2
C
Veja Figura 7-8 para a arquitetura I2C
Figura 7-8 Arquitetura I2C
7.7
TCON
O integrado Controle Timing esta no SSB (conceito “Forward
Integration” ). Veja figura 7-9 para o diagrama em bloco
sistema TCON.
Figura 7-9 Sistema diagrama em bloco TCON
MT5392
NVM
7605
10k
+3V3_SW
10k
22R
22R
OSDA0 (J30)
OSCL0 (J29)
SDA-MAIN
SCL-MAIN
Ambilight
μ
Controller
7801
100R
100R
4k
7
+3V3_SW
4k
7
47
48
AMBI_SDA
AMBI_SCL
OSDA1 (K30)
OSCL1 (K29)
HDMIMUX
7900
22R
DDC_SCL
DDC_SDA
OSDA2 (AJ10)
OSCL2 (AK10)
67
68
40
27
100R
ForDebugging
100R
10K
10K
+3V3_SW
4k
7
+3V3_SW
4k
7
1R
1R
TUNER_SDA
TUNER_SCL
100R
FRONTEND_SDA
FRONTEND_SCL
100R
15p
15p
TUNER
1205
12
13
L28
L29
47p
5
6
10p
10p
EEPROM
TFT – LCD Panel
Mini - LVDS
Control
Signals
+3V3
+ 1V2
VGH (+35V)
VGL (
−
6V)
+12V
LVDS
(10bit)
Timing
Controller
Power
Block
Gamma
Reference
Voltage
Source Drive IC
Gate Drive
IC
MTK
LCD Panel
TCON
Main Platform
SSB
+ 15.6V