94
LC4.9E AB
7.
Circuit Diagrams and PWB Layouts
SSB: Scaler Interface
S
CALER INTERFACE
TO
S
CALER
FROM HERCULE
S
RE
S
RE
S
FOR PDP ONLY
NC
(PDP)
NC
FROM EPLD
TO TOP CONNECTOR
S
TO EPLD
TO EPLD
3
A0
3
3
A05
3
A04
7A01
4A0
3
3
A06
2A0
3
5V DC 5V PWM
3
V
3
DC
3
V
3
PWM
BACKLIGHT CONTROL
3
90R
-
1K
Y
-
10K
1
u
3
90R
-
1K
Y
-
0R
-
-
-
-
-
Y
10K
1
u
-
-
-
-
Y
0R
-
RE
S
RE
S
RE
S
RE
S
FOR UFD ONLY
RE
S
ERVED
4A01 F
3
4A02 B6
4A0
3
D6
4A04 E4
4A05 F6
4A06 F
8
5A00 E
3
6A01 F
8
7
8
01-
8
A2
7A00 E
3
7A01 C6
7A02 E6
7A0
3
E
8
IA00 C7
IA0
3
F6
IA05 B
8
IA06 C6
IA07 B6
IA0
8
E2
IA09 E2
A
B
C
D
E
F
2A00 D
3
2A01 E2
2A02 E2
2A0
3
C7
2A12 F6
2A1
3
D
8
3
A00 E2
3
A01 E2
3
A02 C5
3
A0
3
B6
3
A04 C6
3
A05 C6
3
A06 C7
3
A07 E2
3
A0
8
E2
3
A10 F6
3
A11 E7
3
A1
3
D
8
3
A14 E9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IA09
4A00 F
3
IA0
8
6A01
BZX
38
4-C
3
V9
4A06
+
3
V
3S
TBY
+
3
V
3S
TBY
+5V
7A0
3
BC
8
47BW
100n
2A1
3
3
A1
3
10K
4K7
3
A14
3
A11
4K7
+
3
V
3S
W
10K
3
A0
8
3
A07
10K
IA07
IA05
IA06
4A02
S
HIELD2|DEGRN4
AE11
S
HIELD
3
|DEGRN5
AE1
3
S
HIELD4|DEBLU2
AD14
S
HIELD5|DEBLU5
AF14
B2p|DEBLU
3
AF12
B
3
n|DEGRN7
AF11
B
3
p|DEGRN6
AF1
3
BCn|DEGRN9
AE12
BCp|DEGRN
8
AF10
S
HIELD0|DEGRN2
AC11
S
HIELD1|DEGRN
3
AD11
AE19
A
3
p|GPIO_G06_B4|DORED6
AF20
ACn|GPIO_G06_B7|DORED9
AE20
ACp|GPIO_G06_B6|DORED
8
AE16
B0n|DEBLU9
AF16
B0p|DEBLU
8
AE15
B1n|DEBLU7
AF15
B1p|DEBLU6
AE14
B2n|DEBLU4
AF2
3
A0n|GPIO_G05_B7|DOGRN9
AE2
3
A0p|GPIO_G05_B6|DOGRN
8
AF22
A1n|GPIO_G05_B5|DOGRN7
AE22
A1p|GPIO_G05_B4|DOGRN6
AF21
A2n|GPIO_G05_B2|DOGRN4
AE21
A2p|GPIO_G05_B1|DOGRN
3
AF19
A
3
n|GPIO_G06_B5|DORED7
LVD
S
7
8
01-
8
GM1501-LF-BD
10n
2A12
3
A0
3
IA0
3
4A04
4A00
4A01
100n
2A00
5A00
S
CL1
7
S
DA0
3
S
DA1
6
VCC
8
+
3
V
3S
W
EN
5
GND
4
NC
1
2
S
CL0
7A00
PCA9515ADP
100p
2A02
100p
6
8
R
2A01
3
A01
3
A00
6
8
R
1K0
3
A05
+5V
S
WI
3
A04
S
I2
3
01D
S
-T1
3
1
2
1K0
3
A02
7A01
IA00
2A0
3
4A0
3
1
u
0
10K
3
A06
4A05
10K
BC
8
47BW
7A02
3
A10
BACKLIGHT_DIM
BUF_ENABLE
S
DA_DMA_BU
S
1_DI
S
P
S
DA_IO
S
CL_IO
TXB
3
-
TXBC-
TXB2+
TXB2-
TXB1+
TXB1-
TXB0-
TXB0+
S
CL_DMA_BU
S
1_DI
S
P
BACKLIGHT_CTRL
S
TANDBY
S
C_
S
TANDBY
BU_LHT_ADJ1
TXB
3
+
TXBC+
B9
B9
3
1
3
9 12
3
6141.1
G_15
3
51_009.ep
s
0
8
0906
Содержание LC4.9E
Страница 132: ...132 LC4 9E AB 7 Circuit Diagrams and PWB Layouts Layout IBO Zapper Top Side 3139 123 5906 2 F_15270_061 eps 200505 ...
Страница 133: ...Circuit Diagrams and PWB Layouts 133 LC4 9E AB 7 Layout IBO Zapper Bottom Side 3139 123 5906 2 F_15270_062 eps 200505 ...
Страница 134: ...134 LC4 9E AB 7 Circuit Diagrams and PWB Layouts Personal Notes E_06532_013 eps 131004 ...