EN 21
3139 785 31550
Mono Board: Circuit Diagram (Part 2)
11
1
0
13
12
9
8
9
10
VSS
VDDQ
1M-1
DQM
VDD
VSSQ
0
A
BA
1
6
H
0
WE
L
NC
CAS
RAS
7
5
4
3
2
15
14
11
10
CS
CKE
CLK
D
0
1
2
3
4
5
6
7
8
SCL
ADR
0
1
2
SDA
WC
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSS
VDD
0
A
D
5
2
4
RB
OE
CE
7
6
WE
3
1
RP
0
BYTE
2M-1 / 1M-1
NC
A-1
8
9
10
11
12
13
14
15
*
(SHEET1)
T211 C12
T212 C12
T213 C12
T214 C12
T215 C12
T216 D12
T217 D12
T218 D12
T219 D12
T220 D12
T221 D12
T222 D12
T231 F5
T232 F5
T236 A3
T237 B2
T238 F3
T240 D6
7200 A2
7201 D3
7202 E6
7203 F2
T200 E8
T201 G6
T202 B3
T203 B3
T204 E8
T205 E8
T210 C12
3214-4 E1
3227 E8
3229 E8
3231 E8
3233 F3
3234 F5
3235 F6
3236 G5
3237 G5
3238 G6
3240 H2
3241 H3
3244 C11
3245 C11
4201 G2
4202 C10
4203 C10
4204 C10
5200 B3
5201 D6
5202 D7
3210-1 B1
3210-2 D1
3210-3 D1
3210-4 D1
3211-1 D1
3211-2 C1
3211-3 C1
3211-4 C1
3212-1 C1
3212-2 C1
3212-3 C1
3212-4 C1
3213-1 D1
3213-2 D1
3213-3 D1
3213-4 E1
3214-1 E1
3214-2 E1
3214-3 E1
2267 F3
2268 F3
2269 F5
2271 E9
2272 H6
2273 H7
2274 E9
2275 G11
2276 F5
3203 A3
3204 G10
3209 B3
2255 C3
2256 C3
2257 C3
2258 C3
2259 E10
2260 E10
2261 E10
2262 E10
2263 E10
2264 D6
2265 D7
2266 F5
(SHEET1)
# SPDIF
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
A
* OPTIONAL
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
# Refer to Table
B
C
D
E
F
G
H
1201 B12
2110 E10
2252 A3
2253 B3
2254 C3
10R
1
8
*
(SHEET1)
(SHEET1)
(SHEET1)
3210-1
T238
10R
3233
3213-3
10R
3
6
2265
100n
100n
2264
6
D
D
10R
3210-3
3
10R
4
5
3210-2
2
7
3210-4
10R
D
3K3
3203
3212-2
10R
2
7
2263
22p
600R
5201
600R
D
D
5200
16
3238
1K2
9
43
49
28
41
54
6
12
46
52
44
39
15
36
40
18
1
14
27
3
50
51
53
5
7
8
10
11
13
42
20
21
17
37
38
19
2
4
45
47
48
24
22
35
25
26
29
30
31
32
33
34
7201
1M X 16 X 4
DRAM
F
IS42S16400A-7TLI
23
100n
D
1
8
2268
3213-1
10R
22p
2274
100n
D
2272
3234
75R
47n
2273
2275
4
5
22p
10R
3214-4
22p
2110
22R
3227
3229
22R
D
22R
3231
2
7
3213-2
10R
100n
2253
2254
100n
2255
100n
T211
4201
10K
3240
100n
2269
D
100n
2266
D
D
D
10K
3236
5202
600R
4
7
T200
1
2
3
6
5
8
3
6
(2Kx8)
F
EEPROM
7200
M24C16-RDW6
2
7
10R
3211-3
8
10R
3211-2
3212-1
10R
1
T205
T204
T202
T203
T210
8
9
T231
D
19
2
20
21
3
4
5
6
7
1
10
11
12
13
14
15
16
17
18
T237
1201
21FMN-BTRK-A
6
3214-3
10R
3
16V
1
8
2258
47u
3211-1
10R
3235
22R
2262
22p
2252
D
100n
4203
4
5
4202
8
10R
3213-4
3214-1
10R
1
10R
3214-2
2
7
3212-3
3
6
10R
4
5
10R
T222
3212-4
T221
T219
D
T217
T218
T215
T216
T213
T214
T212
3245
10K
2271
22p
10K
3204
47u
16V
2276
2267
T201
100p
3211-4
4
5
D
10R
T232
2260
22p
T240
10
28
15
12
37
27
46
11
33
35
38
40
42
44
30
32
13
14
7
47
26
29
31
34
36
39
41
43
45
17
16
9
23
22
21
20
19
18
8
25
24
6
5
4
3
2
1
48
6
VD+
23
[FLASH]
2Mx8/1Mx16
7203
M29W160ET70
15
RXP5
25
RXP6
26
SCL|CCLK
28
SDA|CDOUT
1
SDOUT
18
U
20
VA+
RMCK
10
RST_
9
RXN0
5
RXP0
4
RXP1
12
RXP2
13
RXP3
14
RXP4
3
EMPH_
FILT
8
H|S_
24
INT
19
OLRCK
17
OMCK
21
OSCLK
16
RERR
11
7202
CS8415A
AD0|CS_
2
AD1|CDIN
27
AGND
7
DGND
22
T236
T220
3209
3K3
10K
3237
3241
33R
4204
2259
22p
22p
2261
D
10K
3244
2256
100n
100n
SCL_DAC
D
2257
PCM_SCLK
PCM_LRCK
PCM_MCLK
PCM_LR
PCM_LsRs
+3V3_D
AMP_RST
Erro_Det
+3V3_D
PW_DN_
TD
SPDIF_IN
+5D
+5D
+3V3_FL
+5D
+3V3_D
+3V3_D
+3V3_D
SPDATA
SPLRCK
SPBCK
SPMCLK
+3V3_D
SCL_DAC
SDA_DAC
DQ(0:15)
MA(6)
RAS
CS
DCKE
DCLK
BA1
BA0
WE
CAS
MA(0:11)
MA(4)
MA(3)
MA(2)
MA(1)
MA(0)
MA(11)
MA(10)
MA(9)
MA(8)
MA(7)
MA(5)
DQ(9)
DQM1
DQM0
DQ(12)
DQ(13)
DQ(14)
DQ(15)
DQ(2)
DQ(3)
DQ(4)
DQ(5)
DQ(6)
DQ(7)
DQ(8)
DQ(0)
DQ(1)
DQ(10)
DQ(11)
A(21)
+3V3_FL
PWR
A(0:21)
A(20)
AD(0:7)
AD(5)
AD(6)
AD(7)
PRD
+3V3_FL
+3V3_FL
PCE
AD(0)
AD(1)
A(0)
AD(2)
AD(3)
AD(4)
A(19)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(1)
A(2)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
SCL_DAC
SDA_DAC
+5VS
SP_RST
SDA_DAC
PCM_MIC_IN
PCM_MIC_IN
+5VS
PCM_CLfe
TU_SD
TU_SD
+5D
SPDIF_IN
SPDIF_IN
3139_243_32765_a2_sh130_a2.pdf_010406
7.
Circuit Diagram and PWB Layout