Philips HDD100, Руководство по обслуживанию

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4.1 CY7C68013 Pin Descriptions
Table 4-1. FX2 Pin Descriptions
[5]
128
TQFP
100
TQFP
56
SSOP
56
QFN Name Type Default Description
10 9 10 3 AVCC Power N/A Analog V
CC
. This signal provides power to the analog section of
the chip.
13 12 13 6 AGND Power N/A Analog Ground . Connect to ground with as short a path as possi-
ble.
19 18 16 9 DMINUS I/O/Z Z USB D– Signal . Connect to the USB D– signal.
18 17 15 8 DPLUS I/O/Z Z USB D+ Signal . Connect to the USB D+ signal.
94 A0 Output L 8051 Address Bus . This bus is driven at all times. When the 8051
is addressing internal RAM it reflects the internal address.
95 A1 Output L
96 A2 Output L
97 A3 Output L
117 A 4 Output L
118 A 5 Output L
119 A 6 Output L
120 A 7 Output L
126 A 8 Output L
127 A 9 Output L
128 A 10 Output L
21 A11 Output L
22 A12 Output L
23 A13 Output L
24 A14 Output L
25 A15 Output L
59 D0 I/O/Z Z 8051 Data Bus . This bidirectional bus is high-impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The data
bus is active only for external bus accesses, and is driven LOW in
suspend.
60 D1 I/O/Z Z
61 D2 I/O/Z Z
62 D3 I/O/Z Z
63 D4 I/O/Z Z
86 D5 I/O/Z Z
87 D6 I/O/Z Z
88 D7 I/O/Z Z
39 PSEN# Output H Program Store Enable . This active-LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x2000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
34 28 BKPT Output L Breakpoint . This pin goes active (HIGH) when the 8051 address
bus matches the BPADDRH/L registers and breakpoints are en-
abled in the BREAKPT register (BPEN = 1). If the BPPULSE bit in
the BREAKPT register is HIGH, this signal pulses HIGH for eight
12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal re-
mains HIGH until the 8051 clears the BREAK bit (by writing 1 to it)
in the BREAKPT register.
99 77 49 42 RESET# Input N/A Active LOW Reset . Resets the entire chip. This pin is normally tied
to V
CC
through a 100K resistor, and to GND through a 0.1-
µ
F ca-
pacitor.
Note:
5. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and
in standby.
PIN DESCRIPTIONS OF IC CY7C68013