Philips FW-V720, Руководство по обслуживанию

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8-4
8-4
VISBA VIDEO PC PROCESSOR CHIP PIN DESCRIPTION
Name Number I/O Definition
VDD 1, 31, 51 I Voltage supply for 3.3 V.
RAS# 2 O DRAM row address strobe (active low).
DWE# 3 O DRAM write enable (active low).
DA[8:0] 12:4 O DRAM multiplexed row and column address bus.
DBUS[15:0] 28:13 I/O DRAM data bus.
RESET# 29 I System reset (active low).
VSS 30, 50, 80, 100 I Ground.
YUV[7:0] 39:32 O Y is luminance, UV are chrominance data bus for screen video interface. YUV[7:0] for 8-
bit YUV mode.
VSYNC 40 I/O Vertical sync for screen video interface, programmable for rising or falling edge.
HSYNC 41 I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
CPUCLK 42 I RISC and system clock input.
CPUCLK is used only if SEL_PLL[1:0] = 00.
PCLK2X 43 I/O Pixel clock; two times the actual pixel clock for screen video interface.
PCLK 44 I/O Pixel clock qualifier in for screen video interface.
AUX[7:0] 54, 52, 53,
49:45
I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
LD[7:0] 62:55 I/O RISC interface data bus.
LWR# 63 O RISC interface write enable (active low).
LOE# 64 O RISC interface output enable (active low).
LCS[3,1,0]# 65,66,67 O RISC interface chip select (active low).
LA[17:0] 87:82, 79:68 O RISC interface address bus.
VPP 81 I Digital supply voltage for 5 V.
ACLK 88 I/O Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz).
AOUT/
SEL_PLL0 89 O Dual-purpose pin. AOUT is the audio interface serial data output
I Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK
for the Visba:
00 = bypass PLL.
01 = 54 MHz PLL.
10 = 67.5 MHz PLL.
11 = 81 MHz PLL.
ATCLK 90 I/O Audio transmit bit clock.
ATFS/
SEL_PLL1 91 O Dual-purpose pin. ATFS is the audio interface transmit frame sync.
I Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK for the Visba.
See the SEL_PLL0 pin above for the settings.
DA9/DOE# 92 O Dual purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column
address bus.
AIN 93 I Audio interface serial data input.
ARCLK 94 I Audio receive bit clock.
ARFS 95 I Audio interface receive frame sync.
TDMCLK 96 I TDM interface serial clock.
TDMDR 97 I TDM interface serial data receive.
TDMFS 98 I TDM interface frame sync.
CAS# 99 O DRAM column address strobe bank 0 (active low).
ES3880 VIDEO CD PROCESSOR CHIP
1
VSS
AUX4
AUX3
AUX2
AUX1
AUX0
PCLK
PCLK2X
CPUCLK
HSYNC
VSYNC
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
VDD VPP
LA12
LA13
LA14
LA15
LA16
LA17
ACLK
AOUT/SEL_PLL0
ATCLK
ATFS/SEL_PLL1
DA9/DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0
DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
DWE#
RAS#
VD
D
VSS
RESET# DBUS15 DBUS14 DBUS13 DBUS12
DBUS1
1
DBUS1
0
DBUS9 DBUS8
LD
6
LD
7
LW
R
#
LO
E#
LCS3
#
LCS1
#
LCS0
#
LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA1
0
LA1
1
VSS VDD AUX5 AUX6 AUX7 LD
0
LD
1
LD
2
LD
3
LD
4
LD
5
31
30
51
50
80
81
100
ESS
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
20
Visba ES3880
Video CD PC
100-pin PQFP
Visba Video CD PC Block Diagram
DRAM DMA
Controller
DRAM Interface
Huffman
Decoder
64x32 ROM
32x32 SRAM
Registers
On Screen
MPEG
Video Output
2Kx32 ROM
512x32 SRAM
Processor
RISC
Serial Audio
TDM
Processor
Display
Interface
Interface
AOUT
ARFS
AIN
ATCLK
ACLK
AUX[7:0]
CPUCLK
DBUS[15:0]
CAS#
DOE#
RAS#
DWE#
HSYNC
LCS3#, LCS#[1:0]
LOE#
LA[17:0]
LWR#
LD[7:0]
DA[8:0]
PCLK2X
PCLK
RESET#
ATFS
SEL_PLL[1:0]
TDMCLK
TDMDR
VSYNC
YUV[7:0]
Serial
Audio
Interface
TDM
Interface
DRAM
AUX
Screen
Display
Misc.
Processor
Interface
TDMFS
ARCLK
www.freeservicemanuals.info 1/3/16
Published in Heiloo, Holland.