Philips EM3E, Руководство по обслуживанию, Страница: 50 / 120

Circuit Descriptions and Abbreviation List GB 102 EM3E 9.
The sandcastle pulse from the HOP is fed to pin 1 of the
TOPIC, which is used as reference for timing.
9.8.2 Video Control
After source selection, the HOP controls the signals for
Saturation, Contrast and Brightness. Output is RGB again.
9.8.3 OSD/TXT Control
On pins 35 to 38 the RGB and fast blanking from the OTC
(OSD and TXT) are inserted. The sync signal V
SYNC
) is
derived from the ‘FRAMEDRIVE-“ signal.
9.8.4 Peak White Limiting
On pin 43 there is a Peak White Limiting signal line (PWL). If
the beam current increases, the ‘EHT-info’ voltage will
decrease. Average limiting via R3343/C2333 controls PWL.
9.8.5 Cut-off Control
The following will happen when you switch the TV to
Standby:
1.
The vertical scan is completed.
2. The vertical flyback is completed (the horizontal output is
gated with the flyback pulse, so that the horizontal output
transistor cannot be switched ‘on’ during the flyback
pulse).
3. The ‘slow stop’ of the horizontal output is started, by
gradually reducing the 'on' time at the horizontal output
from nominal to zero (this will take 50 ms).
4. At the same time, the fixed beam current is forced via the
black-current-loop for 25 ms. This is done by setting the
RGB outputs to a maximum voltage of 5.6V.
In the EM3E a 'one-point' cut-off control is used:
A current of 8
m
A (for cut-off) is fed to pin 44 of the HOP. This
is done with a measurement pulse during the frame flyback.
During the 1st frame, 3 pulses are generated to adjust the
cut-off voltage at a current of 8
m
A. With this measurement
the black level at the RGB-outputs is adjusted.
So at start-up there is no monitor pulse anymore. At start-up,
the HOP measures the pulses, which come back via pin 44.
The RGB-outputs have to be between 1.5 V and 3.5 V. If one
of the outputs is higher than 3.5 V or one of them lower then
1.5 V, the RGB-outputs will be blanked.
9.8.6 Geometry control
All geometry control is done via I
2
C and the data is stored in
the NVM (IC7011) of the SSB.
9.8.7 Deflection Control
Line Drive
The Line drive is derived from an internal VCO of 13.75 MHz.
As a reference, an external resonator is used (1301). The
internal VCO is locked with the HD
100
-pulse, which comes
from the PICNIC.
The 'PHI-2' part in the HOP receives the HFB_X-RAY_PROT
(pin 13) to correct the phase of the Line drive. The EHT-info
is supplied to pin 14 (DYN-PHASE-CORR) to compensate
picture breathing depending on the beam current.
Note: This is not used in the EM3E, therefore EHT-
compensation in the SAM menu is put to zero.
Frame Drive
At pins 1 and 2 the symmetrical frame drive signals are
available. The V
SYNC
signal, for synchronisation of the OSD/
TXT, is derived from the ‘FRAMEDRIVE-‘ signal.
East/West Drive
At pin 3, the E/W-drive is available. Pin 4 is a feedback input
for the EHT-info, and is used to prevent pumping of the
picture. The EHT varies also dependent on the beam current.
For wide-screen without load this is 31.5 kV and with load
(1.5 mA) 29.5 kV.
Frame Rotation
For frame rotation, a control voltage is used from pin 25 of the
HOP. Frame rotation is only used in wide-screen sets.
9.8.8 Protections
Flash detection
When a flash occurs, the EHT-info will become negative very
fast. Via R3316/D6304/D6303, TS7303 starts to conduct.
This makes pin 5 of HOP ‘high’. The output (pin 8) is
immediately stopped.
If the H-drive stops, then also pin 5 will become ‘low’ again,
which will reset the flash detection.
A bit (FLS) is set in an output status register, so that the OTC
can see that there was a flash. This FLS-bit will be reset
when the OTC has read that register.
HFB protection
If the HFB is not present, it this detected via the HOP. The
OTC puts the TV into protection and reads a register in the
HOP. An error code is generated.
9.9 Synchronisation (diagram B2, B3 & B4)
The HIP video processor provide the vertical and horizontal
sync pulses V
A
and H
A
. They are synchronised with the
incoming CVBS signal. Then these pulses are fed to the
PICNIC, where they are doubled to be synchronous with the
100 Hz picture. The outgoing pulses, VD
100
and HD
100
, are
fed to the HOP, which supplies the vertical and horizontal
drive pulses and the 100 Hz (2f
H
) sandcastle pulse.
The VD
100
pulse from the PICNIC is inverted by TS7304 to
the V
D
signal. The OTC is synchronised on the HFB pulse
from the CRT and on the V
SYNC
from the HOP, for the
synchronisation of TXT/OSD/EPG
When no CVBS is offered to the video processor, the V
A50
and H
A50
pulses are switched ‘off’ by the HIP, and the pulses
are generated by the PICNIC (to assure a stable OSD).
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