HW Straping
NFCEN2 is no Function
ICE mode Enable
OLT TEST MODE
RTC TEST
ABIST mode
JTAG2 PIN selection
[FESFDI:SFCS]=1 TEST CPU
[FESFDI:SFCS]=2 TEST VDAC
[FESFDI:SFCS]=3 TEST SCAN
MODE
RS232 Ports
RS232 CONNECT
VFD/IR Port
STB_5V
O
D
L
_
3
3
D
D
V
A
B
T
S
_
OI
3
C
C
V
VCC3IO_S
AVDD33_LDO
AVDD10_LDO
ETTXD2
ETCOL
ETRXD0
ETRXCLK
ETCRS
ETRXE
R
ETTXCLK
ETRXDV
ETTXEN
ETRXD2
ETTXD1
ETTXD0
ETRXD1
ETTXD3
ETMDC
ETMDIO
ETRXD3
VSTB
VCLK
VDATA
UARXD
UATXD
P_RESET#
IR
RESET#
ETTXD0
ETTXD1
SDA
SCL
ETRX
E
R
UATXD
UARXD
EXT_INTR_3
EXT_INTR_3
SDA
SCL
A_MUTE_M
HPD_MCU
+5V_
M
C
U
IR
V_SDA
V_CLK
SDA
CEC_M
RESET_MCU_FB
HPD_MCU
+5V_
M
C
U
HDP_MCU
VSTB
VCLK
SCL
CEC_M
VDATA
A_MUTE_M
3.3V
RESET_MCU_FB
+5V_
M
C
U
HPD_MCU
V_S
T
B
V_CLK#
V_DATA
SFCK
5
NFWEN
5
NFCEN2
5
ETRXD0
1
0
ETRXCLK
1
0
ETCRS
10
ETTXCLK
10
ETTXD1
10
ETRXE
R
1
0
ETTXD2
10
ETMDIO
1
0
ETRXDV
1
0
ETMDC
10
ETTXD3
10
ETRXD2
1
0
ETCOL
1
0
ETRXD1
1
0
ETTXD0
10
ETTXEN
10
ETRXD3
1
0
RESET
#
1
,5,10
SCL
5,9
SDA
5,9
NFALE
5
AMUTE
4,9
NFCEN
5
A_MUTE_M
9
CEC_M
4
SDA
5,9
SCL
5,9
RESET_MCU_FB
1
+5V_
M
C
U
4,9
HPD_MCU
4
CEC_M
4
RESET_MCU_FB
1
HPD_MCU
4
+5V_
M
C
U
4,9
HPD_MCU
4
A_MUTE
_
M
9
NFREN
5
FESFDI
5
3.3V
1,2,4,5,7,9,10,11
VCC3IO_STB
3.3V_VCC
3.3V_VCC
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V_VCC
3.3V_VCC
3.3V_VCC
3.3V
3.3V
3.3V
TP3
6
3
C342
100pF
TP111
TP113
J2
CON14P-2.0
CONS14-
X
P
1
2
3
4
5
6
7
8
10
11
12
13
14
9
R421
NC
R390
NC/10K
C339
100pF
TP106
C384
NC
R419
10K
R422
10K
R393
10K
R97
0
C385
NC
R411
NC/10K
C341
100pF
C340
NC/5p
TP107
FB359
0ohm
C391
0.1uF
C389
0.1uF/16V
R94
10
K
R98
0
R397
4.7K
C343
100pF
R398
10K
R429
10K
R405
10K
TP114
R423
4.7K
C337
100pF
R91
0
C338
100pF
R414
NC/10K
TP108
R389
NC/10K
TP3
6
4
U100D
MT8530_DDR2
J33
G35
J37
K36
H38
C37
H34
F36
B38
A43
A41
B40
C39
A39
F38
B42
C41
C43
D40
D42
E39
D38
E37
A37
D36
D34
B34
A35
G33
B36
E35
F34
VCC3IO_STB
VCC3IO_STB
AVDD33_LDO
AVSS33_LDO
AVDD10_LDO
ETCOL
ETCRS
ETMDC
ETMDIO
ETRXCLK
ETRXD0
ETRXD1
ETRXD2
ETRXD3
ETRXDV
ETRXER
ETTXCLK
ETTXD0
ETTXD1
ETTXD2
ETTXD3
ETTXEN
ETTXER
UARXD
UATXD
VSTB
VDATA
VCLK
LCDRD
IR
RESET_
OPWRSB
C387
NC
R404
10K
TP104
R92
0
CB16
0.1uF
C344
100pF
C388
0.1uF
TP109
XP10
4x1 W/HOUSING
1
2
3
4
D456
1N4148/SMD
C386
0.1uF
R428
10K
R400
10K
TP112
FB358
0ohm
R394
10K
R413
NC/10K
R410
NC/10K
R399
10K
R338
10R
R424
4.7K
R420
NC
FB360
FB/0603
TP105
R395
NC/10K
TP110
R402
10K
R95
0
R406
NC/10K
Main Unit--Decoder Board Circuit Diagram
18-6
18-6
Содержание BDP7500B2
Страница 19: ...9 2 Fig D3 Fig D6 Fig D7 Fig D4 Fig D5 Cabinet Disassembly Instructions A06 A05 A02 A04 A04 A08 A03 ...
Страница 27: ...Main Unit MCU Board Layout Diagram 15 2 15 2 TOP Layout Bottom Layout ...
Страница 29: ...Main Unit VFD Display Board Layout Diagram 16 2 16 2 TOP Layout Diagram Bottom Layout Diagram ...
Страница 43: ...Main Unit Decoder Board Layout Diagram Top Layout Diagram 18 13 18 13 Bottom Layout Diagram ...
Страница 44: ...Main Unit Power Board Circuit Diagram 19 1 19 1 ...
Страница 45: ...Main Unit Power Board Layout Diagram Top Layout Diagram 19 2 19 2 Bottom Layout Diagram ...
Страница 47: ...Main Unit Output Board Layout Diagram Top Layout Diagram Bottom Layout Diagram 20 2 20 2 ...
Страница 48: ...Main Unit Exploded View 21 1 21 1 ...
Страница 49: ...22 1 Packing Exploded View ...
Страница 53: ...8 Restart the player test with CD DVD BD disc If ok the repair procedure is finished ...