Philips BDL46xxE, Руководство по обслуживанию

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Philips BDL46xxE 16
internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized
as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of a BankActivate command which is
then followed by a Read or Write command. The EM636165 provides for programmable Read or Write
burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode
register, the system can choose the most suitable modes to maximize its performance. These devices
are well suited for applications requiring high memory bandwidth and particularly well suited to high
performance PC applications.
12. National Semiconductor LM1881 Video Sync Separator
The LM1881 Video sync separator extracts timing information including composite and vertical sync,
burst/back porch timing, and odd/even field information from standard negative going sync NTSC,
PAL*, and SECAM video signals with amplitude from 0.5V to 2V p-p. The integrated circuit is also
capable of providing sync separation for non-standard, faster horizontal rate video signals. The
vertical output is produced on the rising edge of the first serration in the vertical sync period. A default
vertical output is produced after a time delay if the rising edge mentioned above does not occur within
the externally set delay period, such as might be the case for a non-standard video signal.
13. NXP PCF8563 RTC
The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption. A
programmable clock output, interrupt output and voltage-low detector are also provided. All address
and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400
kbits/s. The built-in word address register is incremented automatically after each written or read data
byte.
14. ST TSH340 Video Buffer
The TSH340 is a video buffer featuring a gain of 6dB. A large bandwidth of 300MHz for only 9.4mA of
quiescent current allows the TSH340 to achieve a gain flatness of 220MHz. Its structure features a
very high slew rate of 540V/
μ s minimum guaranteed by test. Associated to a very good THD these
characteristics are particularly intended in the high quality video systems. The TSH340 is available in
tiny SOT23-5 and SO8 plastic packages for size saving consideration.
15. Pericom PI5C3253 Dual 1-of-4 FET Multiplexer / Demultiplexer
Pericom Semiconductor's PI5C3253 is a Dual 4:1 Multiplexer / demultiplexer with three-state outputs
that is pinout compatible with the PI74FCT253T, 74F253, and 74ALS/AS/LS 253. Inputs can be
connected to outputs with low on resistance (5
ȍ ) with no additional ground bounce noise or
propagation delay.
16. ESMT M13S128324A DDR SDRAM
17. ATMEL AT24C64AN EPROM
The AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device's cascadable
feature allows up to 8 devices to share a common twowire bus. The device is optimized for use in
many industrial and commercial applications where low power and low voltage operation are essential.
The AT24C32A/64A is available in space saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead
EIAJ SOIC, 8-lead Mini-MAP (MLP 2x3) and 8-lead TSSOP packages and is accessed via a 2-wire
serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.