Philips Semiconductors
Application note
AN1651
Using the NE/SA5234 amplifier
1991 Oct
15
configuration and its output is squared to swing approximately 5V,
the standard TTL level. Again common-mode biasing is passed
along from each of the stages up to the last in order minimize parts
and simplify circuit layout. The final stage is a simple buffer
amplifier to allow the receiver to drive a low impedance long wire
line of 600
Ω
to 900
Ω
resistance. Some rise time response
adjustment may be required. This is easily achieved following stage
three by using R
T
-C
T
to limit the rate of change of the signal voltage
prior to the buffer. Note that the last stage acts as a zero-crossing
detector. This maximizes noise immunity by allowing a transition
only after the third stage output voltage has risen above 2/3V
CC
.
Phase inversion may be accomplished, if the logic level signals are
polarity reversed, by making stage 3 inverting and AC coupling the
input signal with a sufficiently large capacitor to reduce droop.
Stage 3 must then be biased by connecting its non-inverting node to
bias point ‘A’. This provides a 2.5V threshold for the proper
switching operation of the stage. However, care must be taken not
allow the network’s time constant to become code dependent as to
the average low frequency signal components or errors will result in
the output signal.
The advantage of this particular circuit is that it has the simplicity of
single supply operation along with the capability of a large output
swing making it fully TTL compatible
REFERENCES:
Philips Semiconductors. Linear Data Manual, Volume 2 : Industrial.
Sunnyvale: 1988.
Wong, Alvin K. Companding with the NE577 and NE578..Philips
Semiconductors Applications Note AN1762 : September 1990.
1
2
3
4
5
6
7
10
11
12
16
15
14
13
VREF
VCC
GND
COMPIN
BANDGAP
IREF
Σ
Σ
∆
G
∆
G
EXPANDOR
COMP.
GAINCELL
GAINCELL
RECT.
VCC
GND
COMPCAP2
COMPCAP1
GCELLIN
COMPOUT
RECTIN
VREF
EXPOUT
EXPCAP
RECTIN
EXPIN
RECT.
C3
C1
R1*
C2
R2*
C4
10
µ
F
2.2
µ
F
10
µ
F
10
µ
F
C8
C7
C6
R3*
C5
+
+
+
+
+
+
+
10
µ
F
2.2
µ
F
10
µ
F
C9
+
10
µ
F
2.2
µ
F
+
8
9
+
C10
R4
10
µ
F
SUMIN
PWRDN/
PWRDN
C11
1nF
*R1, R2 and R3 are 1% resistors.
30k
30k
10k
10k
10k
10k
10k
5k
10k
8.6k
MUTE
MUTE
TO
PIN 4
NE578
SL00652
Figure 24. Block Diagram of NE578 Test and Application Circuit
