Service Modes, Error Codes, and Fault Finding
5.
Figure 5-3 +8V Protection
5.7.4
DOP Related Protections
The uP reads every 200 ms the status register of the DOP (via
the I2C bus). If a protection signal is detected on one of the
inputs of the DOP, the relevant error bit in the register is set to
“high”. If this error bit is still “high” after 1 s, the OTC will store
the error code in the error buffer of the NVM and, depending on
the relevancy of the error bit, the set will either go into the
protection mode or not.
Horizontal Fly Back Protection
Hardware is employed for the detection of a horizontal
deflection fault. The DOP core generates a hardware interrupt
when consecutive three horizontal flyback pulses are not
received at the HFB input of the DOP block of the ADOC IC.
To avoid false detection, the corresponding interrupt sub
routine checks the status of “NOHFB” status bit in the DOP
core for five times consecutively with an interval of 50 ms
before triggering the protection mode. The response time for
this protection needed is 300 ms.
Figure 5-4 Horizontal Fly Back Protection
X-Ray Protection (Over Voltage, USA only)
Hardware is employed for the detection of X-ray fault. A
hardware interrupt is generated by the DOP core when the
"XPROT" input of ADOC IC is pulled "HIGH" (flyback pulses
are > 27 V_pp).
To avoid false detection, the corresponding interrupt sub
routine checks the status of “XPROT” bit in DOP core for five
times consecutively with an interval of 50 ms before triggering
the protection mode. It should be noted that the “XPROT”
status is not reset on reading. It should be cleared by the
software explicitly.
Once the XRAY protection status is confirmed, the “PRD” bit
has to be set to "1" by software. This enables an automatic stop
of the H-out via Slow Stop initiated by auto-clearing the DFL bit.
Now, the protection mode is activated.
Figure 5-5 X-Ray Protection
Beam Current Protection
A hardware interrupt is generated by the DOP core when the
current at the BCL input of the ADOC IC exceeds the limit.
To avoid false detection, the corresponding interrupt sub
routine checks the status of “BCF” bit in DOP core for five times
consecutively with an interval of 50 ms before triggering the
protection mode. Once the BCL protection status is confirmed,
the “PRD” bit has to be set to "1" by software. This enables an
automatic stop of the H-out via Slow Stop initiated by auto-
clearing the "DFL" bit. Now, the protection mode is activated.
Figure 5-6 Beam Current Protection
Flash Protection
Flash detection is used to shutdown the set only if the Flash
occurs more than 5 times and is persistent. Therefore, this is a
method to protect the set from undue electrical stress because
of picture tube flashes. The flash detector circuitry uses the
"EHT_INFO" signal as input. Its output is connected to the
"FLASH" input of the DOP block of the ADOC.
When the "FLASH" input is pulled "HIGH", the ADOC’s
horizontal drive output stops immediately and the “FPR” status
bit of the DOP core is set to "1". The status is latched until
readout. With the absence of any other disturbances, the
horizontal drive output will restart after the "FLASH" input is
"LOW" again. No software interaction is required in this case.
The “FPR” bit has to be readout by polling at an interval of 500
ms. If the “FPR” status bit has been set to "1" for more than 5
times consecutively, then the protection mode has to be
triggered. Setting the “FPR” bit for less than 5 times by the
"FLASH" input does not need to trigger the protection mode
(shutting down of the H-drive should be enough).
FLASH
DOP
ADOC
BCL
NOHFB
XPROT
ADC
KEYBOARD
MPIF_IRQ
MIPS CORE
CL 36532058_059.eps
091003
-Ve
Threshold
+Ve
Threshold
Switch
Switch
+8V
Switch
Inverter
Voltage
devider
Signal
conditioning
-Ve
Threshold
EHT-INFO
HFB_X-RAY-
Signal
conditioning
MPIF
ASUP
Detection by MPIF. ASUP status bit will set to
High if +8V falls below threshold level.
-Ve
Threshold
+Ve
Threshold
Signal
conditioning
Switch
Switch
MPIF
+8V
Voltage
divider
FLASH
DOP
ADOC
BCL
NOHFB
XPROT
ADC
KEYBOARD
MPIF IRQ
MIPS CORE
CL 36532058_056.eps
091003
EHT-INFO
HFB_X-RAY-
Switch
Inverter
-Ve
Threshold
Consecutively check for 5 cycles
for the presence of flyback pulses
Signal
conditioning
-Ve
Threshold
+Ve
Threshold
Signal
conditioning
Switch
Switch
MPIF
+8V
Voltage
divider
Signal
conditioning
FLASH
DOP
ADOC
BCL
NOHFB
XPROT
ADC
KEYBOARD
MPIF IRQ
MIPS CORE
CL 36532058_055.eps
011003
EHT-INFO
HFB_X-RAY-
Switch
Inverter
-Ve
Threshold
>27Vp-p
If EHT is too high at defined level,
the switch will set XPROT to High
(over voltage).
-Ve
Threshold
+Ve
Threshold
Switch
Switch
MPIF
+8V
Switch
Inverter
Voltage
divider
Signal
conditioning
-Ve
Threshold
FLASH
DOP
ADOC
BCL
NOHFB
XPROT
ADC
KEYBOARD
MPIF IRQ
MIPS CORE
CL 36532058_058.eps
011003
EHT-INFO
HFB_X-RAY-
Signal
conditioning
When beam current is too high, at
defined level and will set BCL input
to=<1.2V, e7365. This bit is checked
for 5 consecutive cycles to ensure
not caused by other defect
(i.e flash-over).
Содержание A02E
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