Circuit Descriptions
7.
Figure 7-36 TCON block diagram
Notes to figure
:
•
LVDS receiver: converts the data stream back into RGB
data and SYNC signals (Vsync, Hsync, Data Enable - DE)
•
ODC: Over Drive Circuit - to improve LC response
•
Data Path Block: the video RGB data input to data path
block is delayed to align the column driver start pulse with
the column driver data
•
Timing Control Function: generates control signals to
column drivers and row drivers (Source Enable - SOE,
Gate Enable - GOE, Gate Start Pulse - GSP).
For an overview of the TCON DC/DC converters, refer to figure
.
Figure 7-37 TCON DC/DC converters
1
8
770_2
3
9_100127.ep
s
100127
LV D
S
R e c e iv er
LV D
S
R e c e iv er
Ve rtic a l & H o rizo n ta l
Tim in
g
g
e n e ra tio n
D a ta
P a th
B lo c k
(L in e
B u ffer)
M ini-LVD
S
Tran
s
mitter
M ini-LVD
S
Tran
s
mitter
O P C
(Optimum
Power
Control)
(Over
Drive
Circuit)
(Dynamic
Contra
s
t
Control)
O D C D C A
F
o
rm
a
tt
e
r/
S
e
ria
liz
e
r
S
p re a d
S
p e c tru m
S
D R A M
I
2
C
S
lav e
I
2
C
M a
s
ter
R O M
E E P R O M
1 6 bit
H
s
y n c
/
V
s
ync
DE
S S
C L K
(
S
p re a d
S
pectrum C lo c k)
RLV P /N
Ri
g
ht h alf
data
Gate D river
C trl
S
i
g
n al
s
S
ource D river
C trl
S
i
g
n al
s
R 1 A ~E
R 1 C L K
R 2 C L K
R 2 A ~E
M in i-
LVD
S
Output
LVD
S
Input
Control
S
i
g
nal
Output
T im in
g
C o n tro lle r IC
1
8
770_240_10012
8
.ep
s
10012
8
D C /D C
C o n tro lle r
+ 1 2 V
L G D
S
H P
W h ere U
s
ed
V G H
+ 2
8
V
+
3
5 V
To G a te D riv e r
s
(G a te
H i
g
h Vo lta
g
e )
V G L
-6 V
-6 V
To G a te D riv e r
s
(G a te
L o w Vo lta
g
e )
V c c
+
3
V
3
+
3
V
3
Tim in
g
C o n tro lle r IC
S
u p p ly Vo lta
g
e
V c c
+ 1 V
8
+ 1 V 2
Tim in
g
C o n tro lle r IC
S
u p p ly Vo lta
g
e
Vre f
+ 1 6 V
+ 1 5 V 2
G a m m a R e fe renc e
Vo lta
g
e
V d d
+ 1 6 V
+ 1 5 V 6
S
o u rc e D riv e r
S
u p p ly
Vo lta
g
e