Philips 50PUS7605/60, Руководство по обслуживанию

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9-4-15 HDMI-SOC-ARC
0 : n o s u p p o r t N A N D
1: bootup on NAND
BS 4, 3 =
00: STBC boot from SPI, CPU from NAND 2 Row
01: STBC & CPU both boot from NAND 2 Row
10: STBC & CPU both boot from NAND 3 Row
11: STBC boot from SPI, CPU from NAND 3 Row
B S 1 2 _ B o o t u p f r o m N A N D
B S 9 B S 1 2 B S 1 3 B S 1 5 B S 1 8 B S 1 9 B S 2 0
R4512 10K 5%
R
45
1
9
10
K
5
%
R
45
1
7
10
K
5
%
R4514 10K 5%
R4515 NC/10K 5%
R4524 10K 5%
R4525 10K 5%
B S 2 _ B y p a s s S T B C M a s k R O M
W h e n B S 1 = 0 ,
0: Through STBC MaskROM
1: Bypass STBC MaskROM
0 : n o s e c u r i t y b o o t
1: security boot
B S 9 _ S e c u r i t y b o o t
R
45
32
10
K
5
%
R
45
29
10
K
5
%
R
45
28
10
K
5
%
R
45
30
10
K
5
%
R
45
27
10
K
5
%
BS3
BS19
B S 8 _ S T B C w a t c h d o g
0 0
S T B C S i d e :
0 : U s i n g C P U M a s k R O M
1 : Bypass CPU MaskROM
B S 0 _ B y p a s s C P U M a s k R O M
BS15
BS13
0 0 0
B S 1 5 _ N A N D P a g e s i z e
B S 1 8 _ N A N D E C C M O D E
0 : R S
1: BCH
B S 1 5 =
0: 128 Kbytes
1: 256 Kbytes
N A N D :
B S 1 3 =
0: 2 Kbytes
1: 4 Kbytes
B S 1 3 _ N A N D P a g e s i z e
STBC3V3
0
0 : N A N D I / O i n S T B C e M M C s i d e ( B S 1 2 = 1 )
1: NAND I/O in ARM CI side (BS12 = 1, BS[4:3] = 00, 11)
or STBC SPI side (BS12 = 1, BS[4:3] = 01, 10)
0 0 0
0 : D e f a u l t d i s a b l e S T B C w a t c h d o g
1: Default enable STBC watchdog
0 1 1
B S 0 =
0: programming using i2c
1: programming using pbus
T e s t M o d e
1
B S 1 5 B S 1 3 B S 1 2 B S 9
0
0
BS20 BS19
BS18
0
0 1 0 0 1 1 1 0 0 1
BS3 BS2
BS1
BS0
STBC and CPU Boot From Nand
BS8 BS4
0: NF/eMMC type internal boot strap enable
1: NF/eMMC type internal boot strap disable
(BS[7:6] = 00, BS8 is external; BS[17:16]=00,BS14=0, BS13,BS15,BS18
are external)
BS19_Internal boot strap for NF/eMMC type
BS3,BS4_Device
CP U S ide :
STBC3V3
STBC Side:
CPU Side:
BS8
BS21
eMMC:
BS13 =
0: EMMC Bus width is 8 bit
1: EMMC Bus width is 4 bit
BS13_eMMC bus width
BS15_eMMC ACK
0: Boot mode wait ACK
1: Boot mode do not wait ACK
0: 26M
1: 13M
BS18_EMMC clk_switch
BS18
BS4
BS3
BS21
BS8 6
BS4 6
BS3 6
BS9
BS8
BS15 6
BS13 6,20
BS12 6
BS9 6
BS21 6
BS20 6
BS19 6
BS18 6
BS19
BS18
BS15
BS13
BS12
BS20
Updated on 2019/2/27
BS20_NAND I/O
Updated on 2019/2/27
BS4, 3 =
00: STBC boot from SPI, CPU boot from eMMC
01: STBC & CPU both boot from eMMC
10: STBC & CPU both boot from SPI
11: Reserved (same 00)
0: Disable
1: Enable
BS11_Turnkey Security
B S 1 0 _ S P I F l a s h s c r a m b l e
0 : D i s a b l e
1: Enable
I n t e r n a l
Bootstrap
B S 2 1 _ J T A G p r o t e c t i o n m o d e
0 : o p e n m o d e ( i f O T P - J T A G = 0 )
1: password protect mode
S T B C B o o t F r o m S P I , C P U B o o t F r o m e M M C
BS4
B S 0 B S 1 B S 2
B S 1 _ S T B C B o o t S t r a p O p t i o n
BS3
0: Boot from STBC
1: Boot from CPU, bypass STBC.
BS4
BS12
BS9
BS8
BS20