Philips 50PFL3707, Руководство по обслуживанию, Страница: 39 / 85

9-7
3. Digital Signal Process Block Diagram
PL12.4BBLD
DIGIT
AL MAIN CB
A UNIT
IC3101
(DIGIT
AL SIGNAL PR
OCESS)
LCD MODULE ASSEMBL
Y
CN3906
LV
-OD1(-)
38
LV
-OD1(+)
37
LV
-OD0(-)
40
LV
-OD0(+)
39
LV
-OD2(-)
36
LV
-OD2(+)
35
LV
-OD3(-)
30
LV
-OD3(+)
29
LV
-OCLK(-)
33
LV
-OCLK(+)
32
LV
-ED1(-)
22
LV
-ED1(+)
21
LV
-ED0(+)
23
LV
-ED2(-)
20
LV
-ED2(+)
14
LV
-ED3(-)
13
LV
-ED3(+)
29
LV
-ECLK(-)
17
LV
-ECLK(+)
16
LV
-ED0(-)
24
DIGIT
AL
SIGNAL PR
OCESS
HDMI-IN1 HDMI-IN2
JK3717
D
A
T
A0(+)
ARC D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK
7
14
9 4 6 1 3
10 12 16 15
7 9 4 6 1 3
10 12 16 15
JK3715
CLOCK(+) CLOCK(-)
D
A
T
A(0-15)
ADDESS(0-13) D
A
T
A(16-31)
ADDESS(0-13)
HDMI-IN3
7 9 4 6 1 3
10 12 16 15
JK3716
AU
D
IO
DECODER
HDMI I/F
HDMI SW
T
O
VIDEO/A
UDIO
BLOCK DIA
GRAM
VIDEO DECODER
VIDEO SIGNAL
AUDIO SIGNAL
D
A
T
A(0-7)
IC3102
(NAND FLASH MEMOR
Y)
IC3401
(DDR3 SDRAM)
IC3402
(DDR3 SDRAM)
A/D CONVER
TER
SW
V
G
A-R-IN
V
G
A-G-IN
V
G
A-B-IN
COM-VIDEO-Pr-IN COM-VIDEO-Pb-IN COM-VIDEO-Y/CVBS-IN
DEMODULA
T
O
R
/MPEG DECODER
A
U
DIO I/F
DIF-OUT1 DIF-OUT2 IF-A
GC
IF-A
GC
V
G
A-HSYNC
V
G
A-VSYNC
V
G
A-HSYNC
V
G
A-VSYNC
LV
D
S
T
X
AMP(L)-OUT AMP(R)-OUT SPDIF
ARC-MUTE
Q3002
B
U
FFER
Q3003
B
UFFER
Q3004
MUTE
A
U
DIO(L)-IN
A
U
DIO(R)-IN
D
A
T
A0(+)
D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK CLOCK(+) CLOCK(-) D
A
T
A0(+)
D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK CLOCK(+) CLOCK(-)
AB9 AA9
Y18
AA17
Y17
AA15 AA14 AC
10
AB11 AD13 AE13 AD10
AD15
AE15 AE16 AF16 AE17 AF17 AE14 AF14 AA24 AB25 AA22 AE23 AF23 AE24 AF24 AE25 AF25 AE22 AF22 AB23 AB22 AE19 AF19 AE20 AF20
AD21
AE21
AD18
AE18 Y21
W21
AB14 AB17
L4 L5 L3 L2 K5 K4 K3 L1 J5 J4 J3 J2
H2 G3 H1 G4 H4 G1 G2 H3
AD6 AE6 AD7