42
7.
Circuit Diagrams and PWB Layouts
SSB: EPLD
DATA
GND
ASDI
DCLK
CS_
VCC
INIT_DONE
CLKUSR
STATUS
2
1
0
CEO
TMS
TCK
TDO
TDI
SCAN
CLK
MSEL
3
ASDO
CSO
DCLK
DATA0
1
0
CE
CONFIG
CONF_DONE
4
3
2
1
0
6
5
4
3
2
VCC
RA
RB
RC
RB-
RC+
RC-
RD+
RD-
RCLK+
RCLK-
PDWN
CLKOUT
PLLVCC
RD
GND
LVDSGND
PLLGND
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
LVDSVCC
RA+
RA-
RB+
FOR DEBUGGING
C
D
E
F
1N01 A8
1N02 D10
1N03 F11
1N05 C5
2N01 A1
2N02 C1
2N03 C1
2N04 C2
2N05 D3
2N06 D3
2N07 D4
2N08 D4
2N09 D4
2N10 C5
2N11 B6
2N12 B6
2N13 B6
2N14 B7
2N15 B8
2N16 D10
2N17 F10
2N18 F11
2N19 F11
2N20 F11
3N01 A2
3N02 A2
3N03 A2
RES
TO SCALER
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
A
B
3N43
3N04 A2
3N05 A3
3N06 A3
3N07 C1
3N08 C2
3N09 B3
3N10 C1
3N11 C4
3N12 A4
3N13 A5
3N14 A5
3N15 A6
3N16 A6
3N17 B6
3N18 B6
3N19 B5
3N20 C5
3N21 D2
USE ONLY
EPLD
TO SCALER
RES
3N22 E2
3N23 E2
3N24 F2
3N25 F2
3N26 D3
3N27 D6
3N28 F8
3N29 D10
3N30 E10
3N31 E10
3N32 E10
3N33 E10
3N34 E10
3N35 E10
3N36 E10
3N37 E10
3N38 E10
3N39 E10
3N40 F10
3N41 F10
3N42 F10
3N43 F10
3N44 F10
3N45 F10
3N46 D9
3N47 D9
4N01 D1
4N02 D1
PIXEL+ SETS
TO TOP CONN.
4N03 D1
4N04 D1
4N05 D1
4N06 D1
4N07 D1
4N08 D1
4N09 D2
4N10 D2
4N11 D2
4N12 D2
4N13 D2
4N14 D2
4N15 D2
4N16 D2
4N17 D2
4N18 D2
4N19 D2
4N20 D2
4N21 D8
4N22 D8
5N01 A7
5N02 C3
5N03 C4
5N04 C4
5N05 C5
6N01 F8
7N01 A2
7N02-1 A4
7N02-2 D6
RES
FOR DEVELOPMENT
RES
RES
7N02-5 D9
7N03-1 C2
7N03-2 C1
7N04 D4
FN01 B3
FN02 B5
FN03 C5
FN04 A7
FN05 A7
FN06 B7
FN07 B7
FN08 A8
FN09 B7
FN10 B8
FN11 D5
FN12 E5
FN13 E5
FN14 F5
FN15 F5
FN16 F5
FN17 F5
FN18 D8
FN19 D8
FN20 F8
FN21 F11
FN22 F11
FN23 F11
FN24 F11
FOR NON-
FN25 F3
FN26 D1
FN27 D1
FN28 D1
FN29 D1
FN30 D1
FN31 D2
FN32 D2
FN33 D2
FN34 D2
FN35 D2
IN01 A2
IN02 B2
IN03 A2
IN04 B2
IN05 B3
IN06 C2
IN07 D3
IN08 C1
IN09 C1
IN10 B3
IN11 B3
IN12 C4
IN13 D4
IN14 D4
IN15 D10
IN16 D10
IN17 D10
IN18 D10
IN19 F8
RES
LVDS IN
INTERFACE
TO EPLD
TO SCALER INTERFACE
B21
1u0
2N03
IN01
FN23
4N10
4N04
IN10
IN08
IN09
30R
5N01
R15
M12
P12
IO_81
IO_82
R12
IO_83
T13
IO_84
R13
IO_85
R14
IO_86
P13
IO_87
T15
IO_88
N10
IO_73
P10
IO_74
R11
IO_75
P11
IO_76
N11
IO_77
N12
IO_78
M9
IO_79
M11
IO_80
P8
IO_65
M10
IO_66
R9
IO_67
T9
IO_68
P9
IO_69
N9
IO_70
R10
IO_71
T11
IO_72
T6
IO_57
R7
IO_58
P7
IO_59
N7
IO_60
R8
IO_61
T8
IO_62
M8
IO_63
N8
IO_64
P5
IO_49
M5
IO_50
M6
IO_51
N5
IO_52
N6
IO_53
P6
IO_54
R6
IO_55
M7
IO_56
IO_41
R2
IO_42
T2
IO_43
R3
IO_44
P4
IO_45
R4
IO_46
T4
R5
IO_47
IO_48
Φ
BANK 4
EP1C12F256C8
7N02-5
FN03
100R
3N24
IN18
FN07
4N14
IO_4
B1
IO_40
N4
IO_5
G5
IO_6
F4
IO_7
D3
IO_8
E4
IO_9
F5
IO_34
N3
IO_35
K5
IO_36
L4
IO_37
R1
IO_38
P2
IO_39
P3
IO_3
C2
L2
IO_27
M1
IO_28
N1
IO_29
M2
IO_30
N2
IO_31
M3
IO_32
L5
IO_33
M4
C3
IO_20
H5
IO_21
J1
IO_22
K2
IO_23
L3
IO_24
K1
IO_25
L1
IO_26
IO_14
F3
IO_15
G3
IO_16
F2
IO_17
E1
IO_18
G2
IO_19
F1
IO_1
D4
IO_2
Φ
IO_10
E3
IO_11
D2
IO_12
E2
IO_13
D1
100R
7N02-2
EP1C12F256C8
BANK 1
3N42
2N01 100n
FN02
100R
3N44
1N03
BM05B-SRSS-TBT
1
2
3
4
5
6
7
2N18
FN26
100p
IN16
100R
3N30
3N35
IN17
100n
2N09
100R
47R
3N16
3N14
10K
6N01
TLMG3100
FN25
4N12
IN05
FN08
3N10
33K
+3V3-IO
4N17
IN13
IN14
FN35
IN12
FN34
FN33
FN32
100R
3N31
FN31
FN09
FN30
FN29
FN28
FN27
FN06
IN04
4N22
4N08
3N11
47R
4N09
2N10
100n
5N02
30R
4N11
4N19
FN19
IN02
4N06
K13
G4
H2
K4
J3
J2
J13
J14
H14
H15
J15
7N02-1
EP1C12F256C8
K3
H4
J4
G1
H1
G16
H16
H3
CONTROL
Φ
FN18
+3V3SW
33K
3N07
3N09
1K0
47R
3N18
2N17
100p
2N14
FN22
2N08
100n
+3V3SW
4N15
2N19
100p
FN24
3N38
+3V3SW
100R
4N05
2N02
100n
+3V3-IO
100p
2N20
3N39
BC847BS
2
6
1
100R
7N03-1
+3V3-IO
4N20
IN15
7N03-2
5
3
4
BC847BS
2
1
4
3
IN11
OC
14M31818
1N05
10K
3N05
30R
5N04
100R
2N06
3N25
100n
FN16
+3V3-IO
FN04
+3V3-IO
3N17
47R
100R
3N29
3N08
10K
3N27
47R
100R
100R
3N34
3N33
41
42
49
50
2
31
40
48
56
1
3
5
6
18
17
20
19
7
34
39
43
45
46
47
51
16
15
53
54
55
27
29
30
32
33
35
37
12
11
38
44
52
8
14
21
13
25
22
24
23
10
9
7N04
THC63LVDF84B
26
4
28
36
RECEIVER
INTERFACE
LCD PANEL
Φ
2
3
4
5
6
7
8
9
FN17
1N01
1
10
2N13
10K
3N06
4N13
100R
3N36
4N21
4N16
3N01
100p
2N16
10K
10K
3N12
5N03
30R
30R
100R
5N05
3N41
100R
3N40
3N23
100R
IN03
IN19
+3V3-IO
2N11
3N28
180R
FN21
FN13
3N03
10K
3N02
10K
4N01
100n
2N07
10K
3N13
7
8
FN10
Φ
SCD
7N01
EPCS4SI8
5
1
2
6
4
3
47R
3N15
4N03
100R
3N22
100R
+3V3-IO
3N32
+3V3SW
100n
3N26
4K7
2N05
FN20
2N12
4N07
2N04
1n0
4N02
FN01
FN15
FN05
3N45
100R
100R
3N47
100R
3N46
100R
2N15
100p
4N18
+3V3-IO
3N37
100R
FN14
IN06
10K
3N04
3N19
10K
+3V3-IO
FN11
3N21
100R
IN07
3N20
6
47R
1N02
B4B-PH-SM4-TBT(LF)
1
2
3
4
5
FN12
LVDSCp
LVDSDn
LVDSCLKn
LVDSDp
LVDSCLKp
TXB1+
TXB1-
TXB2+
TXB2-
TXB3+
TXB3-
TXBC+
TXBC-
BACKLIGHT_DIM
TXB0+
LVDSAp
LVDSAn
TXB0-
LVDSBn
B_RT_PWM
G_RT_PWM
LVDSBp
LVDSCn
R_LB_PWM
B_LB_PWM
G_LB_PWM
R_RB_PWM
B_RB_PWM
G_RB_PWM
CLK_REF
LVDS_PWR_DWN
R_LT_PWM
B_LT_PWM
G_LT_PWM
R_RT_PWM
B_IN(2)
B_IN(1)
B_IN(0)
G_IN(5)
G_IN(4)
G_IN(3)
G_IN(2)
G_IN(1)
G_IN(0)
R_IN(4)
R_IN(5)
R_IN(3)
R_IN(2)
R_IN(1)
R_IN(0)
G_IN(3)
G_IN(0)
G_IN(1)
R_IN(7)
R_IN(5)
R_IN(0)
R_IN(2)
R_IN(1)
PARITY_IN
DE_IN
VS_IN
HS_IN
B_IN(7)
B_IN(6)
G_IN(7)
G_IN(6)
R_IN(7)
R_IN(6)
B_IN(5)
B_IN(4)
B_IN(3)
B_IN(1)
PARITY_IN
DE_IN
B_IN(5)
VS_IN
B_IN(3)
HS_IN
B_IN(2)
G_IN(4)
G_IN(6)
G_IN(2)
R_IN(4)
R_IN(3)
G_IN(7)
B_IN(7)
B_IN(0)
G_IN(5)
B_IN(4)
R_IN(6)
B_IN(6)
PIXEL+_RESET
LED_OUT
SCL_IO
SDA_IO
B20
B20
H_16980_020.eps
230207
3139 123 6145.4 *
For LATAM diversity see table in chapter 10
Содержание 42PFL7312/78
Страница 46: ...46 LC4 8L LA 7 Circuit Diagrams and PWB Layouts Layout SSB Top Side Part 1 H_16980_023a eps 230207 Part 1 ...
Страница 47: ...Circuit Diagrams and PWB Layouts 47 LC4 8L LA 7 Layout SSB Top Side Part 2 H_16980_023b eps 230207 Part 2 ...
Страница 48: ...48 LC4 8L LA 7 Circuit Diagrams and PWB Layouts Layout SSB Top Side Part 3 H_16980_023c eps 230207 Part 3 ...
Страница 49: ...Circuit Diagrams and PWB Layouts 49 LC4 8L LA 7 Layout SSB Top Side Part 4 H_16980_023d eps 230207 Part 4 ...
Страница 51: ...Circuit Diagrams and PWB Layouts 51 LC4 8L LA 7 Layout SSB Bottom Side Part 1 Part 1 H_16980_022a eps 230207 ...
Страница 52: ...52 LC4 8L LA 7 Circuit Diagrams and PWB Layouts Layout SSB Bottom Side Part 2 Part 2 H_16980_022b eps 230207 ...