Philips 42PF5320/10, Руководство по обслуживанию

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Circuit Descriptions, Abbreviation List, and IC Data Sheets EN 133 LC4.9E AA 9.
9.11.4 Diagram B12, Type S9993CT (IC7D03, HDMI Panellink), Reserved
Figure 9-11 Internal block diagram and pin configuration
DAC V CC 1
100-Pin
TQFP
(Top V iew)
N/C
2 DACGND
3
N/C 4
DACGNDR 5
DAC V CCR 6
AnRPr 7
COMP 8
RSET 9
DACGNDG 10
DAC V CCG 11
AnGY 12
DACGNDB 13
DAC V CCB 14
AnBP b 15
GND 16
V CC 17
RS V DL 18
RS V DO 19
RS V DO 20
O V CC 21
PGND2 22
P V CC2
23
PLLIN
24
N/C 25
MC
L
K
O
U
T
26
MC
L
K
IN
27
OG
N
D
28
SP
D
IF
29
SD
O
30
WS
31
SC
K
32
HS
Y
N
C
33
V
SYN
C
34
DE
35
Q2
3
36
Q2
2
37
Q2
1
38
Q2
0
39
V
CC
40
GN
D
41
Q1
9
42
Q1
8
43
Q1
7
44
OG
N
D
45
OD
C
K
46
O
V
CC
47
Q1
6
48
Q1
5
49
Q1
4
50
75
Q1
74
O V CC
73
CSDA
72
Q3
71
Q4
70
Q5
69
Q6
68
Q7
67
Q8
66
OGND
65
O V CC
64
Q9
63
Q10
62
Q11
61
Q12
60
Q13
59
58
57
56
55
54
53
52
51
Q0
V
CC
100
GN
D
99
AG
N
D
9
8
R
X
2+
97
R
X
2-
96
A
V
CC
9
5
AG
N
D
9
4
A
V
CC
9
3
R
X
1+
92
RX
1
-
91
AG
N
D
90
A
V
CC
8
9
AG
N
D
8
8
R
X
0+
87
R
X
0-
86
AG
N
D
85
RX
C+
84
RX
C-
8
3
A
V
CC
8
2
EX
T
_
R
E
S
81
P
V
CC1
80
P
G
ND1
79
OG
N
D
7
8
DS
CL
77
DS
DA
76
CSCL
RS V DL
Q2
RESET#
INT
OGND
V CC
GND
SiI 9993
Block Diagram
Pin Configuration
E_14620_149.eps
170305
HDCP
Decryption
Engine
HDCP
Keys
EEPROM
Registers
----------------
Config u ration
Logic Block
XOR
Mask
V ideo
Color
Space
Converter
Up/Down
Sampling
control
signals
I
2
C
Slave
24
DE
Q[23:0]
DSDA
DSCL
R_EXT
RXC±
RX0±
RX1±
RX2±
IN
T
RESET#
A u dio
Data
Decode
Logic
Block
SPDIF
MCLKOUT
PanelLink
TMDS
TM
Digital
Core
MCLK
Gen
HSYNC
V SYNC
ODCK
SD0
SCK
WS
MCLKIN
Mode
Control
A u x Data
Logic
Block
control
signals
V ideo
DAC
30
AnGY
AnRPr
AnBP b
I
2
C
Slave
CSDA
CSCL
OMPC SETR