Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 146
LC4.31E AA
9.
9.5.3
Diagram B7+B8+B9, Type GM1501 (IC7801, Genesis)
Figure 9-5 Internal block diagram and pin configuration
In fra- red R x
Lo w
n d w i d
D C
B a t
h
A
Pul
s
e W i dth
M odul ator
DDC2Bi
DVI
8
/ 16 bi t v i deo
4: 2: 2/CCIR656
8
/16 /24 b i t
v i deo
( 4 :4 :4 / 4 :2 :2 /
CCIR656)
Te
s
t Patte rn
Gen e rato r
Ul tr a-Rel i abl e
DVI Rx
D V I-C o mp lian t
I nput
T r ip le A D C
and PLL
14.
3
1
8
M H z
Cr y
s
tal
Reference
Ima
g
e
Captur e
and
M ea
s
u re
ment
RealColor
TM
Gr aphi c
s
S
hrink
F ilte r
Clock
Gener a ti on
Frame
S
tore
Contr o l
JT A G GP IO
2- w i re
S
erial I/F
Externa l
ROM I/ F
In tern a l
ROM
TTL/
LVD
S
Tx
Di
s
pl a y
Ti mi n
g
Gen e rato r
O
S
D
C o n t ro lle r
Color Table
RA M
s
Output
Bl ender
Vi deo
S
hrink
F ilte r
M o ti on
Ad a p t .
3
: 2/2: 2
detecti on
Vi deo
Zoom
F ilte r
Gr aphi c
s
Zoom
F ilte r
Ima
g
e
Captur e
and
M ea
s
u re
ment
Int e rnal
RA M
X1
8
6
Mi c r o -
co n t ro lle r
Interfa ce
Para lle l
ROM
IF /exte r n a l
mic r o
A n al o
g
RGB
I nput
Panel Data
/C o n t ro l
DDC2Bi
analo
g
DDR
S
DR A M
I/F
Block Dia
g
ram
Pin Confi
g
uration
A
NC
ADC_
3
.
3
ADC_1.
8
ADC_1.
8
A DC_ DGND
RX C+
DVI _ GND
RX 0 + R
X 1 + R
X 2 +
DVI _ GND LBADC_I N
3
D_GND
B
B L U E - B
L U E +
ADC_
3
.
3
A DC_ DGND
DVI _ GND
RX C-
DVI _ GND
RX 0 - R
X 1 - R
X 2 - REX
T LBADC_I
N 2 D_GND
C
G R E E N - G
R E E N +
S
O G
ADC_AGND
NC
DVI_
3
.
3
DVI _ GND
DVI_
3
.
3
DVI_
3
.
3
DVI_
3
.
3
DVI_
3
.
3
LBADC_I N 1 LBADC_
33
D
R E D - R
E D +
ADC_
3
.
3
ADC_AGND
NC
DVI_1.
8
DVI _ GND
DVI_1.
8
DVI_1.
8
DVI_1.
8
DVI _ GND
LBADC_
RETURN
L B A DC_ GND
E
ADC_AGND ADC_AGND ADC_
3
.
3
ADC_AGND
F
NC
VDDD
33
_
PLL
V
SS
A
33
_
RPLL
VDDA
33
_
RPLL
G
VDDA
33
_
FPLL
V
SS
D
33
_
PLL
T C L K X
T A L
H
VDDD
33
_
S
DD
S
V
SS
A
33
_
S
DD
S
VDDA
33
_
S
DD
S
V
SS
A
33
_
FPLL
J
VDDD
33
_
DDD
S
V
SS
A
33
_
DDD
S
VDDA
33
_
DDD
S
V
SS
D
33
_
S
DD
S
K
RE
S
ETn
AC
S
_
R
S
ET_HD
NC
V
SS
D
33
_
DDD
S
CORE_1.
8
CORE_1.
8
D_GND
D_GND
L
O C M _ I N T 2 O
C M _ I N T 1 AV
S
Y NC AH
S
Y NC
D_GND
CORE_1.
8
D_GND
D_GND
M
O C M _ U D O O
C M _ U D I I
R 0 I
R 1
D_GND
D_GND
D_GND
D_GND
N
V G A _
S
D A V
G A _
S
C L D
V I _
S
D A D
V I _
S
C L
D_GND
D_GND
D_GND
D_GND
P
O C M _ C
S
1 n O C M _ C
S
2 n M
S
TR_
S
DA M
S
TR_
S
CL
D_GND
D_GND
D_GND
D_GND
R
R O M _ C
S
n O
C M _ R E n OCM_
W E n EX
T C L K
D_GND
D_GND
D_GND
D_GND
T
OCMADDR
17
OCMADDR
1
8
OCMADDR
19
OCM_C
S
0n
D_GND
CORE_1.
8
D_GND
D_GND
U
OCMADDR
1
3
OCMADDR
14
OCMADDR
15
OCMADDR
16
CORE_1.
8
CORE_1.
8
D_GND
D_GND
V
OCMADDR
9
OCMADDR
10
OCMADDR
11
OCMADDR
12
W
OCMADDR
6
OCMADDR
7
OCMADDR
8
IO_
3
.
3
Y
OCMADDR
3
OCMADDR
4
OCMADDR
5
IO_
3
.
3
AA OCMADDR
0
OCMADDR
1
OCMADDR
2
IO_
3
.
3
AB
OC M D AT A1
3
O
C M D AT A1 4 OC
M D AT A1 5
IO_
3
.
3
AC
OC M D AT A1 0 O
C M D AT A1 1 OC
M D AT A1 2
IO_
3
.
3
G P IO _ G 09_ B2
(
DE GRN0 )
IO_
3
.
3
DCLK
IO_
3
.
3
G P IO _ G 07_ B2
(
DE RE D4 )
IO_
3
.
3
S
HIELD[1 ]
(DE G RN
3
)
LVD
S
B_
3
.
3
LVD
S
B_ GN D
AD O C M D A T A 9 O C M D A T A 6 O C M D A T A
3
O C M D A T A 0
G P IO _ G 09_ B
3
(
DE GRN1 )
G P IO _ G 0
8
_ B0
(
DORE D0 )
DEN
G P IO _ G 0
8
_ B5
(
DOB L U1 )
G P IO _ G 07_ B
3
(
DE RE D5 )
G P IO _ G 07_ B6
(
DE RE D
8
)
S
HIELD[2 ]
(DE G RN4 )
LVD
S
B_
3
.
3
LVD
S
B_
3
.
3
AE O C M D A T A
8
O C M D A T A 5 OCMDATA2
G P IO _ G 09_ B0
(
DE RE D0 )
G P IO _ G 09_ B4
(
D EBLU 0 )
G P IO _ G 0
8
_ B1
(
DORE D1 )
G P IO _ G 0
8
_ B
3
(
DOGRN1 )
G P IO _ G 07_ B0
(
DE RE D2 )
G P IO _ G 07_ B4
(
DE RE D6 )
G P IO _ G 07_ B7
(
DE RE D9 )
S
HIELD[
3
]
(DE G RN5 )
BC +
(DE G RN
8
)
S
HIELD[4 ]
(DE B L U2 )
AF O C M D A T A 7 O C M D A T A 4 OCMDATA1
G P IO _ G 09_ B1
(
DE RE D1 )
G P IO _ G 09_ B5
(
D EBLU 1 )
G P IO _ G 0
8
_ B2
(
DOGRN0 )
G P IO _ G 0
8
_ B4
(
DOB L U0 )
G P IO _ G 07_ B1
(
DE RE D
3
)
G P IO _ G 07_ B5
(
DE RE D7 )
S
HIELD[0 ]
(DE G RN2 )
B
3
+
(DE G RN6 )
B
3
-
(DE G RN7 )
BC -
(DE G RN9 )
1 2
3
4 5 6 7
8
9 1
0 11 12 1
3
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