Philips 160VW, Руководство по обслуживанию

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HUDSON 9
59
2.2.2 TTL Inputs (Sync-Signals)
The Monitor has to operate up to the following specified TTL-input signals
2.2.3 H- Sync. And V – Sync. Signals at the monitor input
High logic level
:
≥
2.4V
Low logic level
:
≤
0.8V
Rise time : 0.8V ~ 2.4V: < 50ns
Fall time : 2.4V ~ 0.8V: < 50ns
Overshoot
:
≤
0.7V
Undershoot
:
≤
0.7V
2.3 DDC Signals
2.4 Factory Preset Timing
VESA Modes
Horizontal Vertical
Mode Resolution Total
Nominal
Frequency
+/- 0.5kHz
Sync
Polarity
Nominal
Freq.
+/- 1 Hz
Sync
Polarity
Nominal
Pixel
Clock
(MHz)
640x480@60Hz 800 x 525 31.469 N 59.940 N 25.175
640x480@72Hz 832 x 520 37.861 N 72.809 N 31.500 VGA
640x480@75Hz 840 x 500 37.500 N 75.00 N 31.500
800x600@56Hz 1024 x 625 35.156 N/P 56.250 N/P 36.000
800x600@60Hz 1056 x 628 37.879 P 60.317 P 40.000
800x600@72Hz 1040 x 666 48.077 P 72.188 P 50.000
SVGA
800x600@75Hz 1056x625 46.875 P 75.000 P 49.500
1024x768@60Hz 1344x806 48.363 N 60.004 N 65.000
1024x768@70Hz 1328x806 56.476 N 70.069 N 75.000
XGA
1024x768@75Hz 1312x800 60.023 P 75.029 P 78.750
WXGA 1360x768@60Hz 1792x795 47.712 N 60.015 N 85.5
WXGA 1366x768@60Hz 1792x798 47.712 N 59.790 N 85.5
Level: L = 0V ~ 0.8V H = 2.4V ~ 5V
Separate sync. Polarity: positive or negative
DDC Serial Data: Pin 12 of 15 pin D-sub connector, TTL-Level
DDC Serial Clock: Pin 15 of 15 pin D-sub connector, TTL-Level
0.8V
0.8V
0V
2.4V
2.4V
< 0.7V
< 0.7V
< 200ns
< 200ns
< 50ns
< 50ns
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