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17” CDT Color Monitor
107T7
21
2.If register bit UCXRAY[2] was set to “1”,micro controller interaction is allowed .If the micro controller doesn’t
interrupt the system, the system will shut down to ldle mode.For any interaction of the micro controller the XRAY
occurrence has to be acknowledged by the micro controller by clearing the bit SY-STATUS[2].The micro controller
take over the control of the handling via software.The actual xray pin status can be read through bit SY-STATUS[1].
Quartz Oscillator(pin45,pin46)
The quartz oscillator circuit is available on pins XTAL1(input) and XTAL2(output) and works together with an
external 48MHz 3
rd
overtone quartz. As a result the quartz oscillator is always running on 48MHz.Other quartz
crystal frequencies than 48 MHz cannot be used.External capacitors on XTAL1 and XTAL2 are not allowed.
B+ Control Function Block
The B+control block of the SAA4849P has the same behaviour as the TDA4856 with adapted threshol voltages.
The circuit allows the user to choose the trigger edge of the HDRV signal and the polarity of the output stage via
I
2
C-Bus.
The B+ control function block of the SAA4849P consists of an Operational Tran conductance Amplifier(OTA), a
voltage comparator, a flip-flop and a discharge circuit. This configuration allows easy application for different B+
control concepts.
HPLL
The horizontal part contains a PLL,which works over the full frequency range from 25kHz to 140 kHz. This range
can be reduced by a ower and an upper frequency limit(Write Once Registers HPMAX and HPMIN).Via I
2
C bus the
number of 48MHz clock cycles is sent through the register. The slewing speed during mode change is also
programmable in a write once register (HSLEW)
After the clocks for the HPLL are switched on, the HPLL starts with a fixed freerunning frequency of 60 kHz. The
H-drive pulses are not active and the start up procedure is inhibited. The default setting of register bit HCONTROL [0]
will cause the HPLL to slew ,not switch. to the freerunning frequency defined in the I
2
C register HPFREE( the default
value is also 60 kHz).Independent on H-syncs which are possibly present. the HPLL will slew to that freerunning
frequency. To achieve an always defined starting point for the startup procedure, this procedure cannot be interrupted.
Содержание 107T7
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Страница 48: ...17 CDT Color Monitor 107T7 48 12 PCB Layout 12 1 Main PCB layout ...
Страница 49: ...17 CDT Color Monitor 107T7 49 12 2 CRPC Board layout ...