PEP VM162, Руководство пользователя

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VM162/VM172 Chapter 2 Functional Description
Juli 23, 1997 Page 2- 31 © PEP Modular Computers
2.10.4 IP Interface Controller
The IP interface controller builts the bridge between the local CPU and the IP bus. Therefore, it synchro-
nizes IP bus cycles with CPU cycles and performs the corresponding bus protocols.
Besides, the IP interface controller provides a set of two control registers. Each set is dedicated to one
IP slot. With these control registers reset, interrupt control, bus speed and memory space can be control-
led individually for each IP slot.
Electrically, the IP interface controller consists of a FPGA and external high performance buffers for IP
bus and control signals.
2.10.5 IP Reset Control
By setting/resetting bit 4 of the IP slot control register an IP module can be enabled or disabled at any
time. The Reset Control Bit reflects directly the status on the reset line (low active).
Note: After a board reset (e. g. power up, VME SYSRES, Watchdog) the IP reset line becomes active by
default (low active). Therefore, the Reset Control Bit has to be set to 1 in advance to further operations
with the IP module.
2.10.6 IP Clock Control
After a board reset the IP clock is set to 8 MHz by default. After detecting that the assembled IP module
supports also 32 MHz (by reading information stored within the module’s ID PROM) the IP clock can
be switched to 32 MHz by setting bit 5 of the IP slot control register.
On the IP interface controller there are implemented in parallel separate clock generators and state ma-
chines for the different IP bus speeds. Therefore, each IP slot can operate at its individual bus speed.
2.10.7 IP Interrupt Control
Both IP IRQ lines INT0 an INT1 can be used to generate interrupt requests. By programming the IRQ
level bits the interrupt priority of the corresponding IP slot can be selected in a range of 1 to 7 (low-to-
high priority).
Each IP slot provides two interrupt request lines per definition. Both IRQ lines INT0 and INT1 are sup-
ported per slot by the IP interface controller but, for selecting IRQ priotity there are the following re-
strictions.
-> INT1 IRQ priority can be set only to level 1, 3, 5 or 7.
-> INT0 IRQ priority can be set only to level 2, 4 or 6.
If both IP slots use the same IRQ level, IP slot a has automatically a higher priority than IP slot b.
Note: A separate Interrupt Enable bit for each INT must be set before any IP interrupt can be passed
from the corresponding IP slot to the CPU.
After a board reset the complete IP interrupt control logic is reset by default. That means the Interrupt
Enable bit is cleared as well as the IRQ level bits ( BIT 2-0).