PEP CP351, Руководство пользователя

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CP351 Introduction
ID 18983, Rev. 0101 Page 1 - 8 ® PEP Modular Computers GmbH
• 32-bit PCI interface capabilities on both the local bus (QBUS) and the PCI Bus
• Master and slave capability on both busses
• Decoupled transfer technology: FIFO
• Four user programmable images
• Serial EEPROM interface for plug & play compatibility
• Interrupt generator on PCI and processor bus
• QSPAN control and status register accessible both from PCI and processor bus
Figure 1-3: PCI-to-Local Bridge Functional Block Diagram
1.5.2 PCI-to-Local Interface Block
The QSPAN PCI interface is made up of a PCI Master Module and a PCI Target Mod-
ule. For transfers from Qbus to the PCI Bus the QSPAN provides the QBUS slave chan-
nel. A transfer from the Qbus to the PCI bus is initiated by a dedicated chip select signal
(CSPCI) whereas two independent, progammable slave images access PCI memory
and I/O spaces. Data transfers from Qbus to PCI Bus are either posted (64-Byte FIFO
for zero wait state bursting on the PCI bus) or delayed accesses.
For the transfers from PCI to the Qbus the PCI target channel is used. Two programma-
ble target images can be mapped anywhere in memory or I/O space. The transfers from
PCI to Qbus can also be posted or delayed whereas these transactions are always buff-
ered. Therefore delayed single transfers are buffered in the single transfer buffer, all the
other transfers are buffered in a 64-Byte FIFO. Higher transfer performance can be
reached by the use of the IDMA channel.
For the configuration of the QSPAN`s transfer channels as described above, 4 kBytes of
configuration and status registers are provided, which can be accessed both from PCI
and local side (QBUS).
Further the PCI interface allows the generation of interrupts to the PCI and the QBUS
(one dedicated interrupt pin per side).
PCI Master
Module
QBus Slave
Module
PCI Target
Module
QBus Master
Module
Q-FIFO
I-FIFO
QBus Slave Channel
IDMA Channel
Register
Channel
Interrupter
P-FIFO
PCI Target Channel
PCI Bus
QBus