PEP Modular Computers 15311, Руководство пользователя

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VMEM-F1 Chapter 2 Functional Description
Page 2- 10
© PEP Modular Computers
July 30, 1997
2.6 Ready-to-Busy Transition Interrupt
In some cases, it may be more effective to interrupt the CPU instead of polling the end of an erase or
program operation. The VMEM-F1 therefore provides a facility to generate a VME Level 2 interrupt re-
quest each time the FLASH memory changes from busy to ready status. The interrupt function is con-
trolled by the interrupt control register and interrupt vector register.
Notes
This function is based on the Ready/Busy output of each FLASH chip. All of the pins are connected as
wired-OR. This means that only one FLASH bank should be busy at any one time in order to fetch each
busy-to-ready transition for the interrupt.
With respect to the Ready/Busy status, the whole FLASH is spilt into three 64 MByte clusters. The cor-
responding wired-OR Ready/Busy signals can be read from the board status register.
2.6.1 Interrupt Control Register
Address: Jumper selected A16 base a HEX 87
Format: Byte
Access: Read and write
Value after Reset: HEX 00
Register Description:
IRQEN
0 Ready-to-busy transition disabled
1 Ready-to-busy transition enabled
0 1 2 3 4 5 6 7
Reserved
Reserved IRQEN
Reserved
Reserved
Reserved Reserved
Reserved