Hardware Design 2-5
U18
CACHE TAG SRAM Data SRAM Jumper Setting
Size (U24) Install JP10
8K8 x 1 or 32K8 x 8
256KB 16K8 x 1 or U28,29,32,33 1-2
32K8 x 1 U34,37,41,42
16K8 x 1 or 64K8 x 8
512KB 32K8 x 1 U28,29,32,33 2-3
U34,37,41,42
1 2 3
TAG SRAM
Note:
When you have a cache module to plug into a 160-pin daul
readout connector. You must make sure that cache modules has a
TAG SRAM
(Care must be taken
when you inserting the modules. If
you can't sure whether that is a
COAST
solution modules or not.
Please contact the modules supplier to avoid
burned-out and
damaging
any modules circuits.
)
and take off the Onboard's DIP
asynchronous DATA and TAG SRAM. The BIOS can auto-detect the
type and size of the SRAM modules on display System Configura-
tions before the system boots Operating System.
160
80
1
81
KEY
v
Burst/Pipelined burst/Asynchronous SRAM Modules
JP10
U28
U29
U32
U33
U34
U37
DATA SRAM
U24
2-4 Cache Memory Configuration
The second level (L2) of cache is installed in the motherboard to increase the
system performance. The
P55-IT
supports different type of combinations for the
cache installation. The
COAST
(
C
ache-
O
n-
A
-
ST
ick.
The cache modules has a
TAG SRAM.
) solution provides Onboard flexibility, allowing Onboard to accom-
modate 256KB and 512KB asynchronous, burst and piplined burst SRAM modules.
Jumper JP10 settings is used to Onboard's DIP asynchronous SRAM for differential
such combinations. Please refer to following configurations for the details.
U42
U41
