Panasonic TH58PZ750U - 58" PLASMA TV, Руководство по обслуживанию

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15.43. D-Board (2 of 2) Block Diagram
CSH
SCL2
SID
SCL2
SCSU
CEH
PCK
CEL2
CPH CMH
CLKM
CEL CSL CML CLK
SD
A2
SD
A2
CL
PRCK
SIU
OCK
D9304
D9305
P+3.3V
P+2.5V
D9303
D9300
D9302
P+1.2V
P+5V
D9301
P+5V
P+5V
DATA 14Bit
CLOCK
35
8
CLKU3(-)
43
CLKU0(+)
P+5V
46
D3C,D4A
*CONTOUR CORRE.
U24A
27
45
+5V DET
56
CMH
PDP PANEL SIGNAL PROCESSOR
42
67
C24 10
U17A
LEU2
45
*S/P CONV.
HD,VD
2
D4B,D4C
CLR
U1
USL
50
D32
+5V
D12A-D13C
*SF TABLE CONV.
U15C
D8A
D29A-D29C
D9C
RESET
55
DDR-DRAM
SUB FIELD
68
67
46
LEU2
PCK
Q9301
45
51
NOISE NR
26
U23C
DATA
P+5V
62
8
D27C,D28A
5
*DATA DRIVER
TO SC20
64
P+5V
34
ODEU1
IC9300
3.3V->5V
24
*CONTOUR CORRE.
DATA 30Bit
27
PLASMA AI PROCESSOR
U26B
39
DATA PROCESS
53
D
DATA 14Bit
U10A
DATA 4Bit
D3A,D3B
38
MPEG
FORMAT CONVERTER,
DATA CONTROL
6bit
55
59
IC9504
30
D17A-D17C
D6A-D7C
36
DATA
ODEU1
P+3.3V
IC9505
10bit
43
24
+5V
D5A-D5C
67
49 8
OCK
P+5V
58
G
14
59
9
D18A-D19C
U17A
P+2.5V
57
CONT
P+5V
26
C54
CLKD3(-)
58
47
+5V DET
13
D16B,D16C
27
D36 18
P+1.2V
DET
CLKU6(+)
CLK
59
8
23
17
40
CLKD1(-)
128Mbit
14
UML
CLKD0(+)
43
36
D16A
RESET
3.3V->5V
Q9303
67
23
10
28
CLKD3(-)
ODED6
11
DDR-IO
PCK
40
59
D22A
CLKU7(-)
RESET
D35 15
64
CLKU2(+)
63
CEL
9
B
SIU
Q9304
12
CLKU4(+)
59
XRST
66
U7A
P+5V
DET
PCK
60
ODED6
U21C
11
P+5V
50
61
28
66
6
CLRD5
2
CLRD5
CEH
LED5
57
67
68
PROCESSOR
U28A
RESET
C55
CLKU6(+)
30
OCK
66
DATA CONTROL 8bit
10
*SF TABLE CONV.
R
+5V
X9200
SUB FIELD
64
IIC
PCU2
SC_SOS1
P+5V
60
39
IIC
3
SCAN CONTORL
45
7
3.3V->5V
53
CLRD6
(U0A-U9C)
48
50
13
10
3
39
(D16B,D16C,D18A-D21C)
CLKU6(+)
52
DATA 14Bit
NUEL
D15C,D16A
9
IC9401
HD,VD
OCK
D10A
60MHz
DATA 14Bit
R
1
26
3
56
CLKU1(-)
66
IC9402
(D14A-D14C,D15C)
*DATA DRIVER
16
34
P+5V
30
9
ADR
2
BUS SWITCH
CONTROL
UMH
P+5V
(U16A-U17A)
UEH
2
10bit
19
P+5V
5
DATA 30Bit
LED5
33.6MHz
D28B,D28C
61
USH
CLKD5(-)
68
51
12
6
CLKU2(+)
41
P+2.5V
35
19
32
CLKU7(-)
35
LED6
CLOCK
P+5V
58
16
ODED5
I/F
14
39
PLL SYNTHESIZER
27
NUEL
36
37 61
LED6
DATA PROCESS
U9C
19
P+5V
DATA 4Bit
CSH
39
UML
44
+5V DET
61
41
1
U16A
53
ADR
46
67
U0A
(D0A-D9C)
42
CLR
U1
D26A-D26C
CLKD2(+)
33
33 49 59
20
B
31
30
15
PCU2
USH
P+1.2V
FLASH
ODEU2
P+5V
P+5V
51
D30A-D31C
DATA
DET
18
31
IC9200
28
U31C
38
DDR-DRAM
60MHz
DET
30
IC9400
8
28
C25
8
(U22A-U31C)
66
47
32
24
CLKD7(-)
U14B
CLKD4(+)
59
U4C
D20A
34
LEDU1
PCD6
29
CLKD2(+)
OCK
RESET
P+2.5V
61
31
68
32Mbit
68
9
U4B
+5V DET
IC9503
+5V
2
43
U29B U12A
USL
DATA 6bit
D24A-D24C
CSL
23
(U10A-U14B)
3
PCU1
SC_SOS2
CONT
(D22A-D31C)
60
ODEU2
D25A-D25C
5
60
6
D20
D33
D17A-D17C
33.6MHz
21
SID
DATA 30Bit
DET
22
3
CONT
+5V DET
10
58
17
3.3V->5V
CLKU2(+)
41
P+5V
CLR
U2
36
13
CLKU4(+)
32
48
P+5V
U19C
U26C
11
CLKU5(-)
67
1
XRST
1
CEL2
C60
(D16A,D17A-D17C)
7
CLKD6(+)
NOISE NR
MPEG
+5V
38
PCD5
UEH
31
128Mbit
60
CLKU1(-)
I/F
U11C
IC9301
CLKU5(-)
1
P+5V
30 9
26
2
CLK OUT
12
PCD5
50
30
2
DATA 13bit
IC9603
D2A-D2C
U1C
VDD
19
(D10A-D15B)
CLKU0(+)
FLASH MEMORY
14
20 4
P+5V
PCU1
CLK OUT
CLKU5(-)
CLKD0(+)
20
D15A,D15B
P+5V
54
64
*S/P CONV.
D23C
64
39.5MHz
8
U22A
PCD6
25
CLKD4(+)
SUSTAIN CONTROL
+5V
(U17B-U21C)
10bit
D0A-D1C
D21C
59
61
68
CLKU1(-)
3
21
CLKU3(-)
U7B
D14A-D14C
C10
52
2
SCSU
10
11
CLR
U2
IC9602
42
66
P+2.5V
26
63
55
17
CLRD6
32
LEVEL SHIFT
U17B
D31
67
34
54
2
38
37
37
IC9802,IC9803
Q9302
+5V DET
CLKU4(+)
D15C
42
U2A
U20A
19 27
P+5V
24
DRV_SOS8
33
45
UMH
41
29
CLKU0(+)
10
CLKD6(+)
1
D11C
P+3.3V
18
24
5
5
(U14C-U15C)
DET
12
CPH
G
48
10
8
DATA 4Bit
55
61
D34
84MHz
3
DATA 4Bit
D14A-D14C
ODED5
P+3.3V
63
38
57
60MHz
20
11
U14C
16
10bit
CLKU3(-)
58
21
CLKU7(-)
U27C
49
D27A,D27B
13
PDP PANEL SIGNAL PROCESSOR
CML
CLKD7(-)
20MHz
22
DDR-IO
50
5
CLKD1(-)
14
42
10bit
64
CL
6
PCK
P+3.3V
39
CLKD5(-)
LEDU1
52
1
39
DATA 30Bit
FLASH
LEVEL SHIFT
10bit
56
18
37
U29A
LEVEL SHIFT
43
LEVEL SHIFT
9
8 17
19
67
U14C
PROCESSOR
31
11
Q9305
2
IC9304
TO C25
TO C24 TO C10
TO C60 TO C54
TO C55
9
16
13
14
7
1
22
12
4
17
6
19
8
18
5
10
21
15
2
3
20
11
TH-58PZ750U
D-Board (2 of 2) Block Diagram TH-58PZ750U
D-Board (2 of 2) Block Diagram
TH-58PZ750U
117