Panasonic TH-L50EM5S, Руководство по обслуживанию

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TH-L50EM5S
27
9 Block Diagram
9.1. Main Block Diagram
S5/ S3.3
CPU BUS
XECS1
XEAS
XNMIRQ
XIRQ1
XERE
XEWE0
DATA
ADR
CTRL
S12/S5 STB5/5VS
S9 REG
S9
(SD-Data-VCC)
S3.3
NAND
Flash
1G
ED[7:0]
Support
Card
< DTV_XRST
XEAS
ECLK
ESZ1
XEWE1
ERXW XEWE0
ESZ0
XEDK
BOOTSWAP
(XRST)
ED[15:0]
EA[7:0],EA[24]
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
Back Light
S12
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
Analog
ASIC
AN34043A
OVP
SOS
Safety
Circuit
< MON_MUTE
< SP_HP_MUTE
STB3.3V/1.2V_REG
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
3.3/1.8
UHS-1
REG
S9-REG
< (SDVOLC)
PWM >
PWM >
S5/ S3.3/ S1.8
SCL
SDA
IF_AGC
IFD_OUT1
IFD_OUT2
DMD_IIC0
Low-IF
XNFCE,XNF
WP
NFCLE,NFAL
E
XNFWE,XNF
RE
NANDRYBY
ED[15:0]
NAND-IF
EA[15:1]
PCOE
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
HSBCLKOUT
HSSYNCOUT
HSVALOUT
HSDOUT[0:7] HS0BCLKIN
HS0SYNCIN
HS0VALIN
HS0DIN[0:7]
PCWAIT
PCCD1
PCCD2
PCREADY
CI-IF
TS-IN TS-OUT
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN[0:7]
DMD
P-IIC2 (For DMD only)
ADC
DTV Decoder
SIF Decoder
VIF Decoder
IIC
DMD-IIC0
DMD-IIC1
Trans Port Decoder CPUBUS NAND-IF
P k
Cross Stream Switch
/ /9'67[
PLQL/9'67[
7&21
LCD
PANEL
LCD
Driver
Driver
Ctrl
(LPL),LPR,POLL,POLR
CPV,GDATA1,GDATA2
INVERTER
or
LED Driver
BL_ON >
BL_SOS <
S3.3
TEMP
SENSOR
P-IIC
S9
INV-LED
For EEFL
PANEL_LED_ON >
Peaks
DCDC
S1.2 S1.5 S1.8 S3.3
STB3.3
STB1.2
STB_XRST
DCDC_EN
DTV_XRST >
SW_OFF_DET >
XRST POWER_DET PWMA
LD
mini-LVDS 156MHz RGB24bit
7pair ( 6data+1clk 156M) Single
Analog AV Input
S9/S5
㻴㻰㻛㼂㻰㻛㻲㻮㻷
㻹㼁㼀㻱
P IIC
A-Chip VDD
Analog AV Input
SIFIN
FEAIN
PC
D/A TUNER
SIF_OUT
Video_OUT
Reset
IEC
ENGS9301D5F
DVB-T
Video_OUT (CVBS)
SIF_OUT
< FE_XRST
A-SW
(Thru)
IPR INS
V-SW
(Thru)
ADC
DAC Analog Video
Processor
Video
Format
Processor
Peaks
sLD2
DAC
DSP
ADC
DDR
S1.5 S1.5
2G-1333Hz
FHD
D-Book6.x Network
EEP
2k
P-IIC
LCD_EEP_WP >
RGB /YPbPr /CVBS /YC
HS,VS
Audio Input
Video Input
AV-SW
R2A11023FT
(W/O EU)
P-IIC
Main Audio L/R
R1, G1, B1, V1
LIN1_R, LIN1_L
AV2
CVBS
Side
Y/V Pb Pr R L
AV1 /
YUV1
V
R
L
I2S
SW
A-Chip
A-D Chip
Internal BUS
USB
S5
USB
Power SW
USB*VBUS >
< USB*OC
S5
S5
USB Memory
EEP
ASIA,Latin
ELSE: 16k
''5,)[ ''5,)[
DDR3+
x16
1G
DDR3+
x32
1G
1333Hz
MKV decording
PWM0LP
PWM0LN
PWM0RP
PWM0RN
AMP
PWM
SPDIF
SW
IIC
STM IIC
STM
0,,,)
86%,)
D-Chip
STB3.3
EEP
16k
STM
EEP_WP >
For STM
S3.3
EEP
EEPROM_WP
P-IIC
For Peaks
SOUND_VCC
PWM
AMP
LV4923V
Optical OUT
OPT
DDC* > STM, Peaks
HPD* < STM
HDMI 5V DET* > STM
HDMI1
Rx*
IECOUT
CLK
GEN
STB3.3
STB1.2
STM-IIC
Serial
STM-Serial0
STM-Serial1
24.576MHz
STM
STM-D Chip
Communication Register
6',)
SDXC
S5
SD Reg
SD_PWR_ON >
< SD_COIN_DET
S3.3
ExFAT: yes
High Speed: no
UHS-I : no
SD-Data-VCC
SDCLK,SDCMD,SDVOLC,
SDDAT[3:0],SDCD,SDWP
< KEY1
POWER KEY
CONTROL PANEL KEY
IIC
P-IIC0
P-IIC1
(P-IIC2)
P-IIC3
Serial
P-Serial0
P-Serial1
P-UART0
P-UART2
DMD IIC
DMD_IIC
0
DMD_IIC
1
XOR
HDMI
Rx
MUX
x3
< KEY3
HDMI_5V_DET STM
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI2
Rx*