Panasonic TH-L32C53T, Руководство по обслуживанию

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TH-L32C53T
31
9 Block Diagram
9.1. Main Block Diagram
S5/ S3.3
S3.3
NAND
Flash
1G
ED[7:0]
XNFCE,XNFW
P
NFCLE,NFAL
E
XNFWE,XNFR
E
NANDRYBY
Support
Card
< DTV_XRST
CPU BUS
XECS1
XEAS
ECLK
ESZ1
XEWE1
ERXW
XNMIRQ
XIRQ1
XERE
XEWE0
ESZ0
XEDK
BOOTSWAP
(XRST)
ED[15:0]
NAND-IF
EA[15:1]
DATA ADR CTRL
ED[15:0]
EA[7:0],EA[24]
PCOE
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
HSBCLKOUT
HSSYNCOUT
HSVALOUT
HSDOUT[0:7] HS0BCLKIN
HS0SYNCIN
HS0VALIN
HS0DIN[0:7]
PCWAIT
PCCD1
PCCD2
PCREADY
CI-IF
TS-IN TS-OUT
PWM0LP
PWM0LN
PWM0RP
PWM0RN
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN[0:7]
ASMCK
ALRCLKO
ABCKO
ASDOUT2
DMD
P-IIC2 (For DMD only)
ADC
DTV Decoder
SIF Decoder
A-SW
(Thru)
IPR INS
V-SW
(Thru)
ADC
DAC Analog Video
Processor
Video
Format
Processor
VIF Decoder
I2S
SW
AMP
PWM
SPDIF
SW
A-Chip
CLK
GEN
A-D Chip
Internal BUS
IIC
DMD-IIC0
DMD-IIC1
Trans Port Decoder CPUBUS NAND-IF
Peaks
sLD2
STB3.3
STB1.2
IIC
STM-IIC
Serial
STM-Serial0
STM-Serial1
24.576MHz
STM
STM-D Chip
Communication Register
2
ETHER
KSZ
ETHER_XRST <
MII-IF
COL,CRS,RXCLK
RXD0,RXD1,RXD2,RXD3
RXDV,RXER,TXCLK
TXD0,TXD1,TXD2,TXD3
TXEN,MDC,MDIO,MDIO_INTL
PHYRSTL,WAKEUP,WUC
USB
S5
USB
Power SW
USB*VBUS >
< USB*OC
S5
S5
USB
Power SW
USB*VBUS >
< USB*OC
S5
S5
USB Memory
U S B -IF
S D -IF
SDXC
S5
SD Reg
SD_PWR_ON >
< SD_COIN_DET
S3.3
ExFAT: yes
High Speed: no
UHS-I : no
SD-Data-VCC
SDCLK,SDCMD,SDVOLC,
SDDAT[3:0],SDCD,SDWP
< KEY1
POWER KEY
CONTROL PANEL KEY
Cross Stream Switch
D-Chip
IIC
P-IIC0
P-IIC1
(P-IIC2)
P-IIC3
Serial
P-Serial0
P-Serial1
P-UART0
P-UART2
DMD IIC
DMD_IIC
0
DMD_IIC
1
XOR
EEP
STB3.3
EEP
16k
STM
EEP_WP >
For STM
S3.3
EEP
EEPROM_WP
P-IIC
For Peaks
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI1
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI2
S3.3
ARC Buffer-SW
ARC_OFF <
Rx*
Rx*
IECOUT
SOUND_VCC
PWM
AMP
LV4923V
DAC
DSP
HDMI
Rx
MUX
x3
ADC
L V DS -T x
m ini-LVDS -T x
T -C ON
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
ASIA,Latin
ELSE: 16k
DDR
D D R -IF x16 D D R -IF x16
S1.5
DDR3+
x16
1G
S1.5
DDR3+
x32
1G
1333Hz
2G-1333Hz
FHD
D-Book6.x Network
MKV decording
LCD
PANEL
LCD
Driver
Driver
Ctrl
EEP
2k
S15.7
P-IIC
T-CON
DCDC
BD81021MUV
P-IIC
GAMMA
DAC
BUF12840
AVDD_ENB >
PANEL_VCC_ON >
LCD_EEP_WP >
(LPL),LPR,POLL,POLR
CPV,GDATA1,GDATA2
P-IIC
Back Light
INVERTER
or
LED Driver
BL_ON >
BL_SOS <
S3.3
TEMP
SENSOR
P-IIC
S9
INV-LED
For EEFL
PANEL_LED_ON >
S12
Peaks
DCDC
S1.2 S1.5 S1.8 S3.3
STB3.3
STB1.2
STB_XRST
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
S12/S5 STB5/5VS
Analog
ASIC
AN34043A
OVP
SOS
Safety
Circuit
< MON_MUTE
< SP_HP_MUTE
STB3.3V/1.2V_REG
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
3.3/1.8
UHS-1
REG
S9-REG
S9
(SD-Data-VCC)
< (SDVOLC)
DCDC_EN
DTV_XRST >
SW_OFF_DET >
XRST POWER_DET
PWM >
PWMA
PWM >
LD
BKSEL
m ini-LVDS 156MHz RGB24bit
7pair ( 6data+1clk 156M) Single
CVBS
RGB /YPbPr /CVBS /YC
HS,VS
Audio OUT L/R
Monitor OUT L/R
Monitor Out L/R
Audio Input
Video Input
Analog AV Input
S9/S5
AV-SW
R2A11023FT
(W/O EU)
㻴㻰㻛㼂㻰㻛㻲㻮㻷
㻹㼁㼀㻱
P-IIC
Main Audio L/R
A-Chip VDD
Analog AV Input
R1, G1, B1, V1
LIN1_R, LIN1_L
LO1_R, LO1_L
HP1_R, HP1_L
LO2_R, LO2_L
VDAC1
SCART Out L/R
(Audio L/R)
SIFIN
FEAIN
AV2
CVBS
PC
Side
R L
Y/V Pb Pr R L
S5/ S3.3/ S1.8
D/A TUNER
SCL
SDA
IF_AGC
IFD_OUT1
IFD_OUT2
SIF_OUT
Video_OUT
Reset
IEC
ENGS9301D5F
DVB-T
DMD_IIC0
Video_OUT (CVBS)
Low -IF
SIF_OUT
< FE_XRST
SOUND_VCC
I2S
AMP
BD5452AM
< KEY3
AV1 / YUV1
AUDIO OUT
2
E E ET T T E E E E H H HE E ER R R
KSZ
COL,CRS R R ,RX R R CLK
RX R R D0,RX R R D1,RX R R D2,RX R R D3
RX R R DV,RX R R ER,TX T T CLK
TX T T D0,TX T T D1,TX T D2,TX T T D3
TX T T EN,MDC,MDIO,MDIO_INTL
P
P PH H HY Y YR R R Y Y Y Y Y Y S S S R R R R R R T T TL L L,W W WA A AK K KE E EU U UP P P,W W WU U UC C C
S
Only C55D
AS A A MCK
ALRC
R LKO K K
ABCKO K K
AS A A DOUT2
SOUND_VCC
I2S
AMP
BD5452AM
Only C55D