Panasonic SJ-MJ55GH, Руководство по обслуживанию

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Pin
No.
Mark I/O
Division
Function
64 SLD0 O Sled control signal output
terminal
65 SLD1 I Sled control signal input
terminal
66 SLD2 I Sled control signal input
terminal
67 SLD3 I Sled control signal input
terminal
68 FOPWMF O Focus PMW output terminal
69 FOPWMR O Focus PMW output terminal
70 TRPWMF O Tracking PMW output
terminal
71 TRPWMR O Ttacking PMW output
terminal
72 FG I Verocity puls signal input
terminal
73 D4M O CLV servo clock
judgement output terminal
(Not used, open)
74 FOK O Focus OK signal output
terminal
75 CL I CPU I/F data transfer clock
input terminal
76 CE I CPU I/F chip enable signal
input terminal
77 DI I CPU I/F data input terminal
78 DO O CPU I/F data output
terminal
79 WRQB O CPU interrupt signal output
terminal
80 INTB O CPU I/F interrupt signal
output terminal
81 DPVCC2 — Power supply terminal for
buffer amp. PWM output
82 LDPWM+ O Buffer amp. Lch PWM
output terminal
83 LDPWM- O Buffer amp. Lch PWM
output terminal
84 RDPWM
+
O Buffer amp. Rch PWM
output terminal
85 RDPWM- O Buffer amp. Rch PWM
output terminal