Panasonic SA-AK52, Руководство по обслуживанию, Страница: 26 / 80

No. Mark I/O Function
52 EFM - EFM signal output
53 PCK - PLL extraction clock output
(fPCK = 4.321 MHz during
normal playback)
54 VCOF2 I/O VCO Loop filter for 33.8688
MHz conversation terminal for
16.9344 MHz crystal mode,
must use other circuit
55 SUBC O Sub-code serial data output
56 SBCK I Clock input for sub-code
serial data
57 VSS I GND
58 X1 IN I Crystal oscillating circuit input
(f = 16.9344MHz)
59 X2 OUT O Crystal oscillating circuit input
(f = 16.9344 MHz)
60 VDD I Power supply input (for
oscillating circuit)
61 BYTCK - Byte clock output
62 /CLDCK - Sub-code frame clock signal
output (fCLDCK = 7.35 kHz
during normal playback)
63 FCLK - Crystal frame clock signal
output (fCLK = 7.35 kHz,
double = 14.7 kHz)
64 IPFLAG - Interpolation flag output (“H” :
Interpolation)
65 FLAG - Flag output
No. Mark I/O Function
1 /RST - RESET output terminal
2 NC - N.C.
3 IN2 I Motor Drive (2) input
4 PC2 I Turntable motor drive signal
(L : ”ON”)
5 NC - N.C.
6 IN1 I Motor driver (1) input
7 NC I N.C.
8 PVCC1 I Power supply (1) for driver
9 PGND1 - Ground connection (1) for driver
10 NC - N.C.
11 D1- O Motor driver (1) reverse-action
output
12 D1+ O Motor driver (1) forward-action
output
13 D2- O Motor driver (2) reverse-action
output
14 D2+ O Motor driver (2) forward-action
output
Pin No. Mark I/O Function
1 DECK2 I Tape mecha condition input
(Half2/Reci_F/Mode/Reci_R)
2 KEY3 I Key 3 input
3 KEY2 I Key 2 input
4 KEY1 I Key 1 input
5 V_JOG_AD I Volume jog A-D detection
input
6 J_JOG_AD I EQ Joy jog A-D detection
input
7 CHG_AD1 I (Open Clamp) Chngr sw A-D
detection input 1
No. Mark I/O Function
66 CLVS - Spindle servo phase
synchronizing signal output
("H" : CLV, "L" : rough servo)
67 CRC - Sub-code CRC checked
output (“H” :OK, “L” :NG)
68 DEMPH - De-emphasis ON signal
output (“H” :ON)
69 RESY - Frame re-synchronizing signal
output
70 IOSEL I Mode switching terminal
71 /TEST I Test input
72 AVDD1 I Power supply input (for
analog circuit)
73 OUTL O Left channel audio signal
output
74 AVSS1 I GND
75 OUTR O Right channel audio signal
output
76 RSEL I RF signal polarity assignment
input
(at "H" level, RSEL="H", at "L"
level, RESL="L")
77 IOVDD I 5V supply input
78 PSEL I Test terminal (connected to
Gnd)
79 MSEL I SMCK oscillating frequency
designation input (“L” :4.2336
MHz, “H” :8.4672 MHz)
80 SSEL I SUBQ output mode select
(“H” :Q-code buffer mode)
No. Mark I/O Function
15 D3- O Motor driver (3) reverse-action
output
16 D3+ O Motor driver (3) forward-action
output
17 D4- O Motor driver (4) reverse-action
output
18 D4+ O Motor driver (4) forward-action
output
19 NC - N.C.
20 PGND2 - Ground connection (2) for driver
21 PVCC2 I Power supply (2) for driver
22 NC - N.C.
23 VCC I Power supply terminal
24 VREF I Reference voltage input
25 IN4 I Motor driver (4) input
26 IN3 I Motor driver (3) input
27 RSTIN I Reset terminal
28 NC - N.C.
Pin No. Mark I/O Function
8 CHG_AD2 I (Position/ bottom) Chngr sw
A-D detection input 2
9 /CDRST O CD reset output
10 STATUS I CD signal processor status
input (INV)
11 SPE I Speana input
12 ST/DO/SQC
K I/O Tuner if data/stereo input and
CD subcode clock output
13 SD I/O Tuner signal detect input
14 SUBQ I CD subcode data input (INV)
15 RDS_CL I RDS clock input
16 RDS_DA I RDS data input
14.3. IC703 (AN8739SBE2) Focus coil/ Tracking coil/ Traverse motor/
Spindle motor driver
14.4. IC600 (M38B79MFA053) Microprocessor
26
SA-AK52