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01
CPU A03
CPU IRN0
CPU A07
VDD 1.5V
CPU D2CLK
VCC1 3.3V
CPU A08
CPU A05
CPU A04
CPU A09
VSS
CPU A10
GND1
TESTM
PLL FMON
TEST6
NC
VSS PLA
VSS PLA
VDD PLA
VDD PLA
VCC2 1.8V
VD I12
VD I04
BUSY BO6
VDD 1.5V
VD I13
DSTB BO5
GND2
VD I09
VD I14
VD I05
BLKEND BO4
VCC2 1.8V
VD I15
VSS
VS I
HS I
GND2
NC
VOCKMDI O
VCC1 3.3V
VCLK O
FRP
GND1
TXBO0 BI7
RXBIO BI6
TXBO1 BI5
RXBI1 BI4
VDD 1.5V
TEST7
EXIRQO BI2
VCC1 3.3V
ABO BCLKO
ABO MCLK
VSS
ABO SDTO
ABO SDTI
GND1
ABO IRCLK
ABO CDTO
VCC1 3.3V
ABO CCLK
ABO CDTI
ABO CSN
VDD 1.5V
ABO BCLKI
ABO LRCKI
CPU BREQN
GND1
CPU A23
CPU A24
CPU BACKN
VSS
CPU A21
CPU A22
VDD 1.5V
CPU A19
CPU A20
VCC1 3.3V
CPU A16
CPU A17
GND1
CPU A18
CPU A13
VDD 1.5V
CPU A14
CPU A15
VSS
CPU A11
CPU A12
VCC1 3.3V
CPU CLK
VSS
GND1
XCPURST
PLL RESN
PLL FOUT
TEST0
VCC1 3.3V
TEST1
TEST2
CL3412
CL3411
CL3410
CL3403
Y DATA20
Y DATA21
Y DATA22
Y DATA23
Y DATA24
Y DATA25
Y DATA26
Y DATA27
C DATA20
C DATA21
C DATA22
C DATA23
C DATA24
C DATA25
C DATA26
C DATA27
INH2
INV2
C DATA27
Y DATA20
Y DATA21
Y DATA22
Y DATA23
Y DATA24
Y DATA25
Y DATA26
Y DATA27
C DATA20
C DATA21
C DATA22
C DATA23
C DATA24
C DATA25
C DATA26
INH2
INV2
CL3464
DSC BACK
WINK END
MEMO END
DSC BUSY
DSC WAKEUP
QR3402
UNR321F00L
(INV.)
CARD CMD
CARD D0
CARD CLK
LB3405
J0JBC0000051
R3413
100
R3495
0
R3412 0
R3411 22
C3416
5P
D W0
DSC DTI
DSC XRST
DSC CLK
DSC DTO
UARTO
D UARTI
D3402 MA2SD2400L
D3401 MA2SD2400L
TMS
TCK
TDI SIF
R3498
1500
R3497 820
R3441 22K
CL3405
CL3402
CL3404
CL3413
R3301 0
R3458 22K
CL3477
CL3406
R3460 47K
R3450 47K
R3488 47K
F A7
F A8
F A5
F A4
F A9
F A10
BREQ
F A23
F A24
BACK
F A21
F A22
F A19
F A20
F A16
F A17
F A18
F A13
F A14
F A15
F A11
F A12
Y DATA14
C DATA14
Y DATA15
Y DATA11
Y DATA16
C DATA15
Y DATA17
INV1
INH1
R3462
47K
C3431
0.01
C3430
0.01
TO SUB CN(A-5/B-5)
<TO VIDEO1>
TO SUB CN(B-6)
TO SUB CN(A-6)
<TO CONTROL/JACK>
TO SUB CN(B-6)
<TO EVR>
TO SUB CN(C-6)
<TO CONTROL>
TO SUB CN(A-6/B-6)
<TO CONTROL>
TO SUB CN(B-6)
<TO CONTROL/JACK>
TO SUB CN(C-6)
<TO JACK>
TO SUB CN(D-5)
<TO EX INPUT>
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B61
B60
B70
B59
B48
B49
B75
B74
B66
B67
B68
B63
B69
B62
B52
B51
B50
B1
C3447
4V47
C3446
0.1
C3450
0.1
A43
A45
A4
A39
A5
A6
A11
A7
A46
A47
A18
A10
A21
A38
A36
A35
A37
A49
A48
A30
A40
A50
A51
A52
A28
A29
A53
:VIDEO MAIN SIGNAL PATH
A34
3.2
0
-
3.2
1.4
3.2
0
3.2
0
3.2
0
1.4
1.4
3 2
0
0
0
3.2
3.2
0
0
0
1 4
0
0
0
0
3 2
0
0
1 4
-
-
-
-
-
3.2
0
0
1.4
3.2
3 2
0
-
0
1.6
3.2
3 2
0
1 4
0
3.2
3.2
3.2
0.1
0.9
-
-
1.7
0
-
-
-
0
-
1.4
0
-
-
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS
DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE
BRACKETS( )ON THIS DIAGRAM IS RECORD MODE.
(SP MODE)
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON THIS
SCHEMATIC DIAGRAM FOR ORDERING.WHEN YOU ORDER
A PART,PLEASE REFER TO PARTS LIST.
NV-GS50KR
SUB(DSC MPEG)SCHEMATIC DIAGRAM
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