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KX-F910BX
CIRCUIT OPERATION
3-2. RESET CIRCUIT
The output from pin 3 of the Reset IC (IC9) resets the gate array (IC1), the modem (IC11), the gate array on the operating
board (IC301), the Port IC (IC151) on the analog board through the IC1.
(1) During to momentary power interruption, a positive reset pulse of 175 msec or more is generated and the system is reset
completely.
This is done to prevent partial resetting and system runaway during power fluctuation.
Circuit Diagram
Timing Chart
about 175 ms
4.3
4.2
4.2
0.8
4.3
0.8
+5
about 175 ms
(2) When pin 3 of the IC9 becomes low level, it will prohibit the RAM (IC3) from changing data.
The RAM (IC3) go into the backup mode, when it is backed up by the lithium battery.
(3) The watch dog timer, built-in the gate array (IC1), is initialized about every 1.5 ms.
When the watch dog error occurs, pin 104 of the gate array (IC1) becomes low level.
The terminal of WDERR signal is connected to the reset line so, WDERR signal works as the reset signal.
102
104
WDERR
101
IC1
R78
IC9
+5V
3
8
1
2
C64
C60
103
RESET
RESET
(TO ANALOG BOARD,
OPERATION BOARD)
(TO MODEM)
Содержание KX-F910BX
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