IEEE1394 MODULE (F3 SUB) BLOCK DIAGRAM
BLK-
7
PHY
SDRAM
1.8MHz
CLK
GEN.
RESET
IC10501 (5)
IC10401 (4)
IC10601 (6)
25MHz
CLK GEN.
X10201, IC10201 (2)
TPB-, TPB+
1, 2
P10301
P10302
X10401 (4)
8 PHY DATA BUS
2 PYH CONTROL BUS
CLK
RAM ADRS 13
RAM DATA 16
RAM CONTROLL
IC10707 (4)
RESET
GEN. &
GATE
IC10705,
10707 (7)
6-12B,
14-21B
TPA-, TPA+
4, 5
TPB-, TPB+
1, 2
TPA-, TPA+
4, 5
UPDAT (0-15)
5-12A,
14-21A
UPADR (1-15)
40A-48A
DVPBDAT (0-7)
41B-48B
DVRECDAT (0-7)
CFNRESET
34A
NPOWERDOWN
NUPCS, NUPRD,
NUPWAIT, NUPBHW,
NUPBLW, BCLK,
NUPINT
2A, 5B,
22A/B,
23A/B,
24A/B
DVPBFRM,
DVPBSSP,
DVREFFRM,
DVRECFRM,
DVRECSSP
37-39A
38,39B
CFCLK
33B
CF DATA
32B
FPGA
DUEL
P10101
P10101
P10101
P1701
P1701
P1701
FROM/TO (F3)
DPROC
BOARD
IEEE1394
CONNECTOR
NRESET
2B
P10101
P1701
Содержание AJ-SD93P/E
Страница 3: ... 3 ...
Страница 4: ... 4 AJ D93MC ...
Страница 5: ... 5 ...
Страница 6: ... 6 AJ YA93P AJ YA94G ...
Страница 8: ... 8 AJ SD93P E ...
Страница 9: ... 9 ...
Страница 10: ... 10 ...
Страница 11: ... 11 AJ YA93P AJ YA94G ...
Страница 12: ...FCD0409NTKK145E466E467 ...
Страница 31: ...INF 18 RF CUE Board COMPONENT SIDE SERVO Board COMPONENT SIDE TP6302 TP6502 TP4102 TP233 TP235 TG6001 ...
Страница 32: ...INF 19 11 INTERNAL SWITCH SETTING The switch setting on the AVIO board part of AJ YA93 is as shown below ...
Страница 65: ...INF 52 14 ERROR MESSAGES ...
Страница 66: ...INF 53 ...
Страница 67: ...INF 54 ...
Страница 68: ...INF 55 ...
Страница 110: ...MECH 32 Figure 3 35 2 Confirm this value ...
Страница 114: ...MECH 36 Figure 3 37 2 Confirm this value ...