PairGain HiGain-ETSI RS UTU 712, Руководство пользователя

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Functional Description 700-712-100-01, Revision 01
12 May 10, 1999 UTU-712 and ETU-762 List 1
Nx64k Serial Data Port
In the Nx64k Auto mode, the LTU sets the HDSL line rate to the frequency of the TT clock received at its Nx64k
serial data port. In the Manual mode, the LTU sets the HDSL line rate to the frequency selected in the LTU console
screen.
Figure 6 further defines each mode of serial data transmission. See “System Configuration” on page 22
for more information on selecting the Manual and Nx64k Auto modes.
Figure 6. Transmission of Serial Data in Manual Mode and Nx64k Auto Mode
The line units provide a V.35, V.36, X.21, or RS-530 compliant connection at the serial data port connector
(referred to as interface type). The appropriate interface type is configured as described in
“System Configuration”
on page 22 . PairGain offers V.35 and X.21 connector adapters (ECA-800 and ECA-801, respectively) to convert
the D25F data port connector on the shelves and enclosures to standard V.35 (M34F) and X.21 (D15F) connectors
(see
“Reference Information” on page 61 ).
Line units are always configured as DCE. Output control signals (CTS, DSR, RLSD) follow the interface standard
or may be forced ON or OFF using the console screen menus. The HDSL cards can be set to respond to or ignore
the input control signals, Local Loopback (LL) and Remote Loopback (RL), for loopback activation.
HDSL Interface
The HDSL interface includes the HDSL framer, which performs HDSL multiplexing and demultiplexing
functions, the transceiver and line interface circuit for the single HDSL pair, and a firmware-controlled
programmable clock, which sets the HDSL line rate at the interface output.
In the transmit direction, the HDSL framer accepts inputs from the serial data port as shown in Figure 5 . The data
is placed on the HDSL pair along with the HDSL overhead bits for presentation to the transceiver. A clock
representing the selected HDSL line rate is introduced to the transceiver, which outputs data on the single-pair
HDSL line. In the HDSL receive direction, overhead bits are stripped and processed, and time slots are output to
the Nx64k serial data interface.
Reversals of Tip and Ring wires are automatically detected and accommodated. The Monitor HDSL Span screen
indicates if the Tip and Ring wires are reversed.
System Timing Circuits
The UTU and ETU units can synchronize to any one of the following timing sources:
•
Nx64K: Serial-data port receive clock.
•
INT: Internal oscillator.
•
HDSL: Recovered clock from received HDSL data.
•
EXT: External 2.048 MHz reference (available only for UTUs in a shelf with a management unit installed).