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ARDWARE

EFERENCE

UIDE

MICRO

LINE

C6713CPU

Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 35

6.4 Pinout of the JTAG Connector

Signal

signal

used for

A1 FPGA_TMS

B1 GND

A2 FPGA_TDI

B2 GND

A3 FPGA_TDO

B3 GND

A4 FPGA_TCK

B4 GND

A5 +3.3

B5 GND

FPGA

A6 not

connected B6 not

connected unused

A7 CPU_EMU0

B7 CPU_EMU1

A8 CPU_TCK_RET B8 GND
A9 CPU_TCK

B9 GND

A10 CPU_TDO

B10 GND

A11 +3.3

B11 not

connected

A12 CPU_TDI

B12 GND

A13 CPU_TMS

B13 /CPU_TRST

DSP

Table 16: Pinout of the JTAG connector

Usually, the JTAG connector is used with an adapter that is part of the development kits. This
adapter provides connectors that are mechanically compatible with the standard development
tools:

•

JTAG emulators (e.g. XDS510 PP Plus, XDS510 USB, XDS560)

•

the Xilinx parallel download cable

DSP JTAG connec tor
(fits TI emulator POD)

FPGA JTAG c onnector

B13

A13

TMS

TDI

TDO

TCK

GND

+3.3V

top view

Figure 7: JTAG adapter for the C6713CPU

Содержание micro-line C6713CPU

Страница 1: ...DE Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 1 Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de Hardware Reference Guide micro line C6713CPU High perf...

Страница 2: ...4 2 3 5 UART RS 232 Interface 14 2 3 6 Temperature Sensor 14 2 3 7 Reset Generator and Watchdog 15 2 3 8 External Flags XF signals 15 2 3 9 Power Supply of the Board 15 2 4 Status LED s 15 2 4 1 User...

Страница 3: ...C Bus Control Register I2C 26 3 10 6 External Flag Register XF 27 3 10 7 Watchdog Register WDG 27 3 10 8 Version Register VER 28 4 BOOT PROCESS AND DEFAULT SETUP OF THE C6713CPU 29 5 USING THE FLASH...

Страница 4: ...on 48 7 2 7 Configuring FPGA I O Behavior When FPGA is not Loaded 48 7 3 Signal Levels and Loads 48 7 3 1 Input Voltage Levels for non FPGA Signals 48 7 3 2 Output Voltage Levels for non FPGA Signals...

Страница 5: ...s 33 Table 15 Pinout summary and signal routing for the McASP interfaces 34 Table 16 Pinout of the JTAG connector 35 Table 17 Factory default configuration summary 46 Table 18 Voltage limits for the C...

Страница 6: ...enced throughout this document in square brackets C6713CPU DSP Development Kit User s Guide 20 C6713CPU_DSP_DevKit_ug pdf This document describes software development for the C6713CPU board using DSP...

Страница 7: ...register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C...

Страница 8: ...mpleted 1 0 Flash File System short description only reference to separate user s guide Mentioned that HPI usage requires FPGA Minor corrections to signal descriptions series resistors RESETOUT pull u...

Страница 9: ...converters for peripheral I O power supply optional ORSYS furthermore offers complete development packages including Code Composer Studio XDS510 JTAG emulator debugger or equivalent types and all nec...

Страница 10: ...HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 10 2 1 Block Diagram of the C6713CPU Figure 1 Block diagram of the C6713CPU...

Страница 11: ...Iss Rev 1 1 Page 11 C9 green LED PLD red LED PLD yellow LED FPGA JTAG connector DSP SDRAM temperature sensor flash memory FPGA PLD micro line connectors Figure 2 Top side of the C6713CPU micro line co...

Страница 12: ...1 2 2 2 JTAG Connector The JTAG connector is used during development of application software or FPGA designs It contains two separate JTAG interfaces one for the DSP and one for the FPGA The DSP JTAG...

Страница 13: ...omatically cleared and has to be loaded before it starts operation This can be done manually by application software or automatically by the Flash File System of the C6713CPU The FPGA can be loaded at...

Страница 14: ...It also contains some register that configure board operation See chapter 3 10 for a description of the PLD registers 2 3 5 UART RS 232 Interface The RS 232 interface is realized inside the FPGA and i...

Страница 15: ...is disabled by default thus no resets will be generated and the watchdog timer does not need to be reset by software Enabling the watchdog timer and resetting it is described in chapter 3 10 7 2 3 8 E...

Страница 16: ...when using multiple peripherals to ensure that all interfaces are available at the same time 2 5 1 Multichannel Audio Serial Ports McASP The McASPs are serial ports optimized for the needs of multi c...

Страница 17: ...custom FPGA design 2 5 5 Multi channel Buffered Serial Ports McBSP The TMS320C6713 DSP provides two independent McBSPs Each port can communicate a full duplex continuous data stream at rates up to 75...

Страница 18: ...ated HPI address and data registers which are not accessible for the DSP Here the DMA auxiliary channel connects the HPI to the DSP memory space On the TMS320C6713 DSP the HPI peripherals shares signa...

Страница 19: ...flexible way to perform continuous data flow without CPU intervention as well as scatter gather transfers The enhanced DMA can perform element transfers with single cycle throughput in the case that t...

Страница 20: ...idually set up The complete memory map is shown in Table 1 For a more detailed memory map of the DSP please refer to 4 address range hex size bytes Description 0000 0000 0002 FFFF 192KB Internal RAM 0...

Страница 21: ...sor s CE0 address space This memory can be used for user applications and or data storage The external SDRAM address space starts at address 8000 0000h regardless of the memory size and ends at 8000 0...

Страница 22: ...ration This means less significant bytes are stored first at lower addresses 8 bit write to memory Data to be stored C code result in memory 12 char 0x8000000 0x12 8000 0000h 12 16 bit write to memory...

Страница 23: ...E3 32B3 8A13 Table 3 default initialization values for the FPGA related CE space registers1 Parameter Value Timing for an EMIF clock of 100MHz bus width 32 bit n a Read set up time 3 EMIF clocks 30 ns...

Страница 24: ...it 4 HWCFG 90100000 RAMSIZE CPUSPEED RESERVED FLASH_A19 FCR 90110000 PROG DONE CFG_EN RESERVED LED 90120000 LED_RED LED_GREEN MCR 90130000 SW_RESET RESERVED CTS_RESET_EN RS232_DRV_EN I2C 90140000 SDA_...

Страница 25: ...nput line of the FPGA This bit only has an effect if CFG_EN is set to 1 Please refer to the FPGA development kit documentation for details During reset the PROG_B signal of the FPGA is active independ...

Страница 26: ...PU over the CTS line of the RS232 interface CTS is considered active when CTS line of the micro line connectors is at a voltage of 3 to 10 V Setting CTS_RESET_EN to 0 enables normal usage of the CTS s...

Страница 27: ...igh by its pull up resistor 3 10 6 External Flag Register XF The C6713CPU provides two digital I O pins called external flags XF0 XF1 These I O pins are available at the micro line connectors They are...

Страница 28: ...n board watchdog is enabled A reset will be generated whenever the watchdog timer expires This bit is set to 0 after a hardware reset and can only be set but not be cleared by application software Thu...

Страница 29: ...settings can be used by the user application so the user does not need to change the settings The default settings are listed below Parameter Value CPU clock 225 MHz 300 MHz Peripheral clock 112 5 MHz...

Страница 30: ...which perform the desired function PC side utilities that connect to the C6713CPU upload the DSP side executables and perform the desired function The Flash File System supports storage and boot sequ...

Страница 31: ...G Iss Rev 1 1 Page 31 6 Description of the micro line Board Connectors 6 1 Location of the Connectors For the micro line connectors Pin 1 is marked by a black square in Figure 6 C9 JTAG connector conn...

Страница 32: ...FPGA 6 7 FPGA FPGA HD6 I O Z RESETIN I FPGA 7 8 FPGA FPGA HD7 I O Z RESETOUT O FPGA 8 9 FPGA FPGA HD8 I O Z RESETOUT O FPGA 9 10 FPGA FPGA HD9 I O Z FPGA DR1 I SDA1 I O Z 10 11 FPGA FPGA HD10 I O Z F...

Страница 33: ...TE0 E13 FSX1 E15 DX1 AXR0 5 E11 CLKR1 AXR0 6 E12 FSR1 McASP0 AXR0 7 E14 DR1 SDA1 E10 CLKS1 I2 C SCL1 E16 Table 12 Pinout summary for the McBSP interfaces shared with Default signal name interface sign...

Страница 34: ...2 AHCLKR0 CLKS0 E19 AFSR0 FSR0 E24 ACLKX0 McBSP CLKX0 E23 AHCLKX0 Timer TINP1 E17 AFSX0 FSX0 E25 AMUTE0 McBSP CLKX1 E13 AMUTEIN0 GPIO interrupt GP5 EXT_INT5 D18 AXR1 7 HD1 BB2 AXR1 6 HDS1 BB23 AXR1 5...

Страница 35: ...9 GND A10 CPU_TDO B10 GND A11 3 3 V B11 not connected A12 CPU_TDI B12 GND A13 CPU_TMS B13 CPU_TRST DSP Table 16 Pinout of the JTAG connector Usually the JTAG connector is used with an adapter that is...

Страница 36: ...1 0 HAS HR W HCS HRD_HSTRB HWR_HSTRB HRDY HINT These signals are routed to the DSP s HPI control lines and have a pull up resistor provided by the DSP Additionally HRDY has a 4 7k pull down resistor a...

Страница 37: ...always becomes active if the C6713CPU board is reset There is no difference whether the reset was caused manually by RESETIN power on a watchdog event software or a under voltage condition In all cas...

Страница 38: ...r a custom FPGA design In default hardware configuration this signal is pulled high by a 4 7K pull up resistor Hardware configuration can also be changed to a pull down resistor see chapter 7 2 4 for...

Страница 39: ...of McBSP1 This transmitter clock can either be supplied by an external clock or can be provided internally and then supplied to the pin If the transmitter port function is not needed CLKX1 can also be...

Страница 40: ...n can be read by accessing the DATIN bit This makes TINP1 also usable as general purpose input pin If configured for McASP usage this pin is the transmit high frequency master clock of McASP0 TINP1 ha...

Страница 41: ...al data line of McASP0 DX0 has a 22R series resistor How to use this pin is described in 4 6 and 7 CLKR0 ACLKR0 This pin has a dual function If configured for McBSP usage this pin is the receiver cloc...

Страница 42: ...sage this pin is the transmit frame sync or left right clock of McASP0 FSX0 has a 22R series resistor How to use this pin is described in 4 6 and 7 XF0 XF1 These pins are dedicated general purpose dig...

Страница 43: ...d E31 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is...

Страница 44: ...ly voltage limits C9 D 3 3 V Voltage Regulator Figure 8 Supplying the C6713CPU with power CAUTION The C6713CPU is not protected against reversed voltage Please be careful when connecting power supply...

Страница 45: ...CPU_HRG Iss Rev 1 1 Page 45 C9 D standard PC RS 232 connector Sub D 9pin socket fits directly into a PC front view 5 6 9 1 TxD connect to PC s RxD RTS connect to PC s CTS CTS connect to PC s RTS RxD c...

Страница 46: ...user and are described in the subsequent paragraphs For changing other settings please contact ORSYS Function default setting DSP clock speed same as DSP speed grade HPI McASP1 HPI micro line pin D30...

Страница 47: ...and vice versa The decision which interface is active is controlled by different components and is not available for modification by the user Default setting is to use the HPI If McASP1 is to be used...

Страница 48: ...ic standards 3 3V LVTTL 2 5V CMOS Exceptions are the RS 232 interface signals Their voltage levels are listed in the individual pin description chapter 6 5 4 CAUTION Do not apply voltages higher than...

Страница 49: ...minimum allowed supply voltage maximum allowed supply voltage C6713CPU 3 25 V 3 35 V Table 18 Voltage limits for the C6713CPU 7 5 Power Consumption The typical power consumption is shown in the follow...

Страница 50: ...s recommended to reserve some more space additionally to the existing micro line connectors of the C6713CPU This space does not necessarily need to be mounted with connectors It is only recommended no...

Страница 51: ...28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 51 2 54 5 71 1 27 5 71 15 24 17 78 5 71 5 71 17 78 2 54 5 08 7 62 2 5 1 27 B AA A BB X P E C D EE 1394 2 1394 1 EGND 16 10 1 1 32 1 5 1 32 1 27 66...

Страница 52: ...ral boards Manufacturer fischer Elektronik www fischerelektronik de xx number of pins 1 32 for single row 2 64 for double row Connector type Part No single row SL LP 1 112 xx G CPU board not stackable...

Страница 53: ...ay HPI host port interface a peripheral of the TMS320C6713 DSP i e id est Latin that is I2 C inter integrated circuit a low speed interface between integrated circuits KB 1024 byte LED light emitting...

Страница 54: ...rence Guide TI SPRU233 9 TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide TI SPRU175 10 TMS320C6713 Errata Sheet TI SPRZ191 11 Manual Update Sheet for TMS320C6000 Peripherals Refere...

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