Orban OPTIMOD 6200, Руководство по эксплуатации

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6-18
TECHNICAL DATA Orban Model 6200
should be removed only by the Orban service department. A chip can be ruined
by static discharge or by damage to its delicate pins.
The EXTAL pin of each DSP chip receives a 6.144MHz clock. All DSP chips use
their internal PLL to multiply this by 12 to operate the chip's internal oscillator
(Fosc) at 73.728MHz. Each DSP chip is reset by the Z-180 via latch IC709. DSP
mode configuration is controlled by the state of the MODA, MODB and MODC
(pins 37, 38, 39) on each chip as the chip is brought out of reset. All DSP chips
are configured to bootstrap via the SHI port. The MODB pin, which also serves as
the IRQB input after leaving the reset state, is forced low prior to bringing the
DSP chips out of reset.
Pins 26, 35, 41 and 42 comprise the DSP host port. Host port communication con-
forms to the SPI format with the Z-180 set up as the master and the DSPs as
slaves. The Z-180 generates the HOSTCK clock signal and provides it to SCK
(pin 26) of each DSP. The Z-180 provides the data on the HOSTTX line tied to
pin 41 of each DSP. The data output (pins 35) of each DSP have tri-state outputs
that are wire-ORed to provide the data on the HOSTRX line sent to the Z-180.
The Z-180 controls the slave select (
SS
) (pin 42) of each DSP via latch IC708.
The
SS
pin is used to enable each of the slaved DSP SPI ports for transfer.
DSP IC700 pins 56 and 57 receive serial audio from the digital and analog inputs.
These are the two input ports of the synchronous serial audio interface (SAI) re-
ceiver internal to the DSP. The two serial audio streams are received simultane-
ously. Both inputs share the same frame clock,
/R L
(48kHz) provided to DSP
IC700 pin 55 and the same bit clock, SCK (6.144MHz) provided to DSP IC700
pin 51.
Communication between DSP chips IC700 (first) through IC707 (last) is one-way,
in series from the first to the last. Two of the on-board SAI peripherals on each
DSP are used to transfer 8 words each per frame chip-to-chip. The I2S communi-
cation protocol (two 32-bit words per cycle of the word clock) is used with the
DSPs as slaves, and the 6200 system clocking as master. Data is sent from the two
transmit data port pins 46 and 47 of one chip to the next chip's receive data port
pins 56 and 57. A 192kHz word clock is provided to the transmit pin 50 and the
receive pin 55. A 12.288MHz bit clock is provided to the transmit pin 49 and the
receive pin 51. The SAI links between DSPs are synchronized to each other (to
align the SAI time slots) by making the first occurrence of all IRQBs coincident,
(controlled by Z180 and external hardware) and having all DSPs initialize their
SAI ports on the first reception of IRQB.
The “analog” and digital outputs are transferred respectively to the D/A and the
output SRC from the last DSP chip (IC707). (“Analog” refers to DSP signal that
ultimately gets converted to analog.)
Power Supply
The power supply converts an AC line voltage input to various power sources used by
the 6200. To ensure lowest possible noise, five linear regulators provide
±
15VDC and