APPENDIX A: ADVANCED CONFIGURATION
PCI-AC48 User’s Guide
21
21
mistic Commands Required for Interrupts
Before a Remote I/O brick can generate an interrupt, the following mistic commands must be
executed before the event being monitored occurs:
•
Set Event Table Entry—An entry must be made instructing the I/O brick to monitor for a
specific event occurrence.
•
Enable Event Table Entry—The event entry must be enabled for scanning by the I/O brick.
•
Set Event Interrupt Status—The event entry interrupt must be enabled.
•
Set System Options—The Global Interrupt Enable bit must be set.
And, of course, the event being monitored must then occur.
An interrupt from an I/O unit is cleared by executing a “Read and Clear Event Latches” command. All
event entries on a specific I/O unit that are set to generate an interrupt should be specified when
reading and clearing, as the interrupt output is cleared by the command.
If more than one I/O unit is set up to generate interrupts, the host CPU must poll each one to
determine which interrupt is active. This can be done with a “Read Event Latches” or “Read and Clear
Event Latches” command. If possible, it is best to put all signals that may generate interrupts into
one I/O unit. This will eliminate the need to poll more than one board and speed up the host CPU
interrupt response time.
For additional information on mistic interrupts, see form #270, the
mistic Protocol User’s Guide
.
How mistic Interrupts Work on the PCI-AC48
The IRQ lines on the Phoenix connector are bidirectional RS-485 links and are normally set as inputs.
They are designed to be used with the IRQ output lines found on mistic Remote I/O bricks. The IRQ
outputs of Remote I/O bricks are RS-485 drivers, which are held in tri-state mode until an interrupt is
requested, at which time the outputs are enabled and set active. The PCI-AC48 receives this signal
and sets the IRQ Line Status bit in the Modem Status Register, and a modem status interrupt is
generated.
mistic interrupts for the PCI-AC48 are tied into Windows interrupts and look like UART interrupts. IRQ
inputs are mapped to the 16C550-compatible CTS signal on each of two UARTs on the PCI-AC48.
The CTS status can be polled by reading the Modem Status Register (MSR), and interrupts can be
enabled using the Interrupt Enable Register (IER) and checking the delta-CTS bit of the MSR register
during the interrupt handler. See the register table on
page 22
for details.
The other interrupt sources in the MSR register (delta CD, delta RI, and delta DSR) have been
disabled on the circuit board by tying the corresponding UART signals to VCC.
The Windows API WaitCommEvent can be used with its EV_CTS bit mask to detect a CTS interrupt.
Building Custom Software Using UART Registers
If you are not using Opto 22 mistic or Optomux systems and instead are writing custom drivers or
modifying software to communicate with the registers on the PCI-AC48’s serial ports, you may find
the
“Register Table” on page 22
helpful.
The PCI-AC48 adapter card uses a 16550-compatible UART from Exar Corporation (Exar product
number XR17C158). For additional register definitions not covered in the table below, see the Exar
document for this product at www.exar.com.
