TX-SR603
X
/603E/8360
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-15
Q282: K4S161622H(16Mb H-die SDRAM)-2/2
PIN LAYOUT
TERMINAL DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Pin
Name
CLK
CS
Chip Select
CKE
Clock Enable
BA
RAS
Row Address Strobe
CAS
WE
Write Enable
L(U)DQM
Power Supply/Ground
No Connection/
Reserved for Future Use
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
This pin is recommended to be left No Connection on the device.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
Power and ground for the input buffers and the core logic.
Enables write operation and row pre-charge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
System Clock
Address
Bank Select Address
Column Address Strobe
Data Output Power/Ground
Data Input/Output
Data Input/Output Mask
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
A0 ~ A10/AP
