SHEET
DATE
DESIGN
DRAWING_No.
TITLE
RMII
SPI0
EMA_D[0:7]
EMA_D[0:7]
SPI
SPI
SPI
SPI
SPI
SPI
SPI
MCK_DSDSLK_PLD
AUXIN1
AUXIN0
DIR
ADC
MDIO
50MHz
USB 1.1
JTAG
UART1
I2C0
DA83_RST
DA830_CS
DataBus
ControlSig.s
DataBus
AddressBus
CS/WE/RE/INT/PME
ControlSig.s
DataBus
AddressBus
DIR_MCK
DIR_MCK
HDMI_SPDIF
HDMI_SBLR
ADSP2_SDTV
ADSP2_LRCK
ADSP2_BCK
ARC_SPDIF
HDMI_SPDIF
HDMI_SPDIF
HDMI_SPDIF
FRONT OPT
OPT1
OPT2
COAX1
COAX2
COAX3
COAX1
COAX3
COAX2
OPT1
FRONT OPT
OPT2
TMDS
ADSP1_LRCK
ADSP1_BCK
ADSP1_SD0
ADSP1_SD1
ADSP1_SD2
ADSP1_SD3
ADSP1_SD4
ADSP1_SD5
Tx+/-
Rx+/-
HDMI_SLR
NAND Controles
NAND Controles
DACRST
DACMUT
DACRST
DACMUT
DACRST
DACMUT
DACRST
DACMUT
DACRST
DACMUT
Lch
HLch
Rch
HRch
Cch
SLch
SBLch
SRch
SBRch
SWLch
SWRch
ADSP2_SDTV
STBPOWER2
ARC_SPDIF
AD.Lch
AD.Rch
TMDS
Tx+/-
Rx+/-
RECOUT0
XMCKO
RECOUT1
ADC clock
DIR_RST
DIR_CS
DIGSDI
DIGSDO
DIGCLK
DIRINT0
ADSP2_SD0
ADSP2_SD1
ADSP2_SD2
ADSP2_SD3
ADSP2_BCK
ADSP2_SD4
ADSP2_SD5
ADSP2_SD6
AUXIN2
NET_BCLK
NET_LRCK
NET_ADAT0
STBPOWER2
ADSP2_LRCK
HDMI_CSW
HDMI_MCK
HDMI_SPDIF
MCLK
MCLK
DACRST
DACMUT
DACCS1
DACCS1
DACCS1
DACCS2
DACCS2
DACCS3
DACCS2
DACMUT
DACRST
WRch
WLch
STBPOWER2
Z2.Lch
Z2.Rch
MCLK
DIR_BCLK
DIR_LRCK
DIR_FLR
HDMI_SBLR
HDMI_CSW
HDMI_SLR
HDMI_MCLK
HDMI_BCK
HDMI_LRCK
HDMI_FLR
ADSP2_SDTV
ADSP2_LRCK
ADSP2_BCK
12.288/11.2896
HZ2DATA_BYPASS
HZ2BCK_BYPASS
HZ2LRCK_BYPASS
HDMIZ2.Lch
HDMIZ2.Rch
AUDIO_IN
Z2DAC_EN
HDMI_MCLK_PLD
HDMI_BCLK_PLD
HDMI_LRCK_PLD
HDMI_AData0_PLD
HMZ2_BCK
HMZ2_LRCK
HMZ2_DATA
HMZ2_DATA
HMZ2_LRCK
+3.3VLG
+3.3VLG
NETMCK
HMZ2_BCK
LRCK_DSDSL
DATA7_PLD
DATA5_PLD
LRCK_DSDSW
DATA1_PLD
LRCK_DSDFR
DATA9_PLD
DATA11_PLD
LRCK_DSDFL
DATA13_PLD
+3.3VHT
DATA3_PLD
BCK_GND_PLD
DGCLK
DGSDO
PLDCS
DIRRST
Z2DACRST
HDMIZ2DAC_MUT
NETZ2DAC_MUT
DACRST
DIR_BCK
DIR_LRCK
DIR_DATA
DIR_BCK
DIR_LRCK
DIR_ADATA0
TMDS
HDMI_BCK
HDMI_LRCK
HDMI_FLR
HDMI_SPDIF
HDMI_SBLR
HDMI_CSW
HDMI_SLR
PLDFRESH
PCM9211
DIR/ADC
MAIN OUT
MPIO_C
I
D
R
A
C
D
McASP0
AXR1_0-11
Q3001
D830K013BZKB400Z
1ST DSP
RECEIVER
HDMI
PORT 0
TMDS RX
PORT 1
PORT 2
M
U
X
M
U
X
Q8301
HDMI RX/SW
FRONT IN
MAIN
Q8151
HDMI RX/SW
PORT 4
X
U
M
X
U
M
X
U
M
PORT 5
PORT 3
PORT 2
PORT 1
TMDS RX
PORT 0
HDMI
RECEIVER
HDMI
RECEIVER
X
U
M
IN4
IN5
IN6
IN7
PORT 0
TMDS TX
SII9573 or SII9575
SII9573 or SII9575
PORT 1
TMDS TX
IN2
IN1
IN3
PORT 4
X
U
M
PORT 5
PORT 3
HDMI
RECEIVER
X
U
M
Audio In0
SUB
(Day-Month-Year)
BLOCK DIAGRAM(DIGITAL AUDIO)
SCHEMATIC DIAGRAM (PART-4)
Audio In1
Audio out1
ANALOG
INPUT
COAX 2
COAX 3
OPT FRONT
OPT1
(FRONT IN)
OPT2
COAX 1
ACTIVE L
74VHC157
Q3301
HD BASE-T
Only Integra
K.Murakami
27-03-2014
5
Model No. TX-NR1030/3030,DTR-60.6/70.6,PR-SC5530,DHC-80.6
SUB
PORT 1
MAIN
TMDS TX
PORT 0
TMDS TX
Q3404
2ND DSP
Q1421
DAC
PCM1795
Q1421
DAC
PCM1795
Q1421
DAC
PCM1795
Q1421
DAC
PCM1795
Q1421
DAC
PCM1795
Q1421
DAC
PCM1795
FR/HR
SL/SBL
WL/WR
SR/SBR
SWL/SWR
C
DSD:FR
DSD:C
DSD:SL
DSD:SR
DSD:SW
DSD:FL
DSD:CLK
ASP
Q4500
R2A15220FP
KYOTOG2H
Q8000
SUB OUT
Main OUT
HDMI TX/OSD
HDCP
SII9573
ZONE2 OUT
DIVIDE
DIVIDE
MPIO_B
Q3361
74LCX125
ACTIVE L
PCM1795
DAC
Q1421
Z2 DAC
Q3371
Q3371
PCM5101
HDMI_Z2 DAC
TMPM361F10FG
VMPU
Q8701
(ADSP2BCK_PLD)
(ADSP2DATA_PLD)
(ADSP2LRCK_PLD)
ON SUBTV OUT
ON HDMI_ZONE2
(ADSP2BCK_PLD)
(ADSP2DATA_PLD)
(ADSP2LRCK_PLD)
ON SUBTV OUT
ON HDMI_ZONE2
ON HDMI_ZONE2(diff)
Hi:CONNECT
2ndDSP Bypass SW
FL/HL
BCK
MCK
LRCK
DA810
PCM5101
Lo:Low
HDMIZ2OUT_SELECT
Lo:SAME
Hi:DIFFERENT
ON SUBTV OUT
Lo:CONNECT
Hi:Hi-z
Hi:CONNECT
Lo:OPEN
OPEN/SHORT SW
Wide DAC
DSD/PCM SW
OPEN/SHORT SW
Hi:CONNECT
Lo:OPEN
OPEN/SHORT SW
Hi:CONNECT
Lo:OPEN
Serial
Parallel
Convert
Q1***
PLD
ALL mount
ALL mount
(DSDFL)
(DSDCLK)
(DSDFR)
(DSDC)
(DSDSW)
(DSDSL)
(DSDSR)
(DSDSL)
(DSDFL)
(DSDSW)
(DSDC)
(DSDSR)
(DSDFR)
(DSDCLK)
(DSDCLK)
(DSDFL)
(DSDSW)
(DSDC)
(DSDSR)
(DSDFR)
(DSDSL)
79
RC-203002
TX-NR1030/5030,DTR-60.6/70.6
PR-SC5530,DHC-80.6
DIGITAL AUDIO BLOCK DIAGRAM
37
RXIN0
3
MPIO_A0
4
MPIO_A1
5
MPIO_A2
6
MPIO_A3
35
RXIN1
33
RXIN2
32
RXIN3
31
RXIN4
30
RXIN5
29
RXIN6
28
RXIN7
47
VINL
48
VINR
20
SCKO
19
BCK
18
LRCK
17
DOUT
7
MPIO_C0
8
MPIO_C1
9
MPIO_C2
10
MPIO_C3
D5
AFSX0/BOOT10
P12
AXR0_14
C5
ACLKX0
M2
AXR1_8
N1
AXR1_5
M1
AXR1_9
M4
AXR1_6
P1
AXR1_3
P2
AXR1_2
R2
AXR1_1
T3
AXR1_0
K3
ACLKX1
K4
AFSX1
L3
AFSR1
L2
ACLKR1
N2
AXR1_4
T4
AXR1_11
N3
AXR1_10
B5
AHCLKX0
M3
AXR1_7
K2
AHCLKX1
24
CLKIN
134
SCK1_IN
135
WS1_IN
136
SD1_IN
128
SD3
130
SPDIF
133
SCK0
131
WS0_OUT
132
SD0
125
MCLK
122
SCK0
121
WS0_OUT
124
SD0
127
SD1
126
SD2
134
SCK1_IN
135
WS1_IN
136
SD1_IN
121
WS0_OUT
122
SCK0
124
SD0
125
MCLK
103
DAI_P11
74
DAI_P13
75
DAI_P19
76
DAI_P01
77
DAI_P02
89
DAI_P10
92
DAI_P20
87
DAI_P06
88
DAI_P09
73
DAI_P07
87
DAI_P05
14
SCKI
6
LRCK
7
BCK
8
DIN1
14
SCKI
6
LRCK
7
BCK
8
DIN1
14
SCKI
6
LRCK
7
BCK
8
DIN1
14
SCKI
6
LRCK
7
BCK
8
DIN1
14
SCKI
6
LRCK
7
BCK
8
DIN1
14
SCKI
6
LRCK
7
BCK
8
DIN1
46
SUBL1
48
SUBR1
B8
I2S_IN_DT0
A9
I2S_IN_WS
A10
I2S_IN_CK
24
MDI
23
MDO
1
INT0
15
MPO0
16
MPO1
25
MC
26
MS
34
RST
39
XTI
40
XTO
77
DAI_P02
92
DAI_P20
87
DAI_P05
89
DAI_P10
88
DAI_P09
74
DAI_P13
75
DAI_P19
76
DAI_P01
101
DAI_P15
100
DAI_P12
94
DAI_P08
95
DAI_P14
96
DAI_P04
97
DAI_P18
98
DAI_P17
99
DAI_P16
14
MPIO_B3
13
MPIO_B2
12
MPIO_B1
11
MPIO_B0
100
DAI_P12
94
DAI_P08
95
DAI_P14
96
DAI_P04
97
DAI_P18
98
DAI_P17
99
DAI_P16
101
DAI_P15
87
DAI_P06
14
DAI_P07
14
DAI_P07
8
DIN1
7
BCK
6
LRCK
14
SCKI
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
92
DAI_P20
1
BCK
2
DATA
3
LRCK
16
SCK
7
VOUT_L
8
VOUT_R
73
DAI_P07
99
DAI_P16
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
14
DAI_P07
2
DATA
3
LRCK
1
BCK
7
VOUT_L
8
VOUT_R
91
PI1/CEC
58
PE7/INT5/SCOUT
14
DAI_P07
76
DAI_P01
75
DAI_P19
77
DAI_P02
74
DAI_P13
87
DAI_P06
89
DAI_P10
77
DAI_P02
92
DAI_P20
87
DAI_P06
77
DAI_P02
88
DAI_P09
87
DAI_P05
73
DAI_P07
PHY
Serial Console
Apple ACP
24MHz
64Mbit 133MHz
SDRAM
EthernetController
w/LocalBus
WiFi/BT
24.576Hz
X1001
11.2896MHz
RJ-45
64Mbit SDRAM
NANDFlash
256Mbit
RJ-45
X1100
24.576MHz
NANDFlash
256Mbit
0
0
0
0
TX-NR1030/3030/DTR-60.6/70.6/PR-SC5530/DHC-80.6
SCHEMATIC DIAGRAMS-05
DIGITAL AUDIO BLOCK DIAGRAM
TX-NR1030/3030/DTR-60.6/70.6/PR-SC5530/DHC-80.6
A
1
2
3
4
5
B
C
D
E
F
G
H
6
7
8
I
J
K