DV-CP702
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
A0-A2
Address Inputs
SDA
Serial Address/Data I/O
SCL
Serial Clock Input
WP
Write Protect Input
Vcc
Power Supply
GND
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data
into and out of the device. The SDA pin is an open drain output and
can be wire-Ored with other open drain or open collector outputs.
The SDA bus requires a pullup resistor to Vcc.
PIN CONFIGURATION
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
A0, A1, A2
The A0, A1 and A2 are the device address inputs.
The IS24C08 only use A2 input for hardwire addressing and a
total of two devices may be addressed on a single bus system.
The A0 and A1 pins are not used by IS24C08. They may be left
floating or tied to either GND or Vcc.
WP
WP is the Write Protect pin.
On the and 24C08, if the WP pin is tied to V
CC
the entire array
becomes Write Protected (Read only). On the 24C16,
if the WP pin is tied to Vcc the upper half array becomes Write
Protected (Read only). When WP is tied to GND or left
floating normal read/write operations are allowed to the
device.
Q2003 : IS24C08-3Z EEPROM
(8K-Bit 2-Wire Serial CMOS EEPROM)
PIN DESCRIPTIONS
DATA
REGISTER
Y
DECODER
EEPROM
ARRAY
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
X
DECODER
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
WORD ADDRESS
COUNTER
nMOS
ACK
Clock
DI/O
7
4
GND
WP
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