DV-SP500
1 DAIN
2 LRIN
3 BCKIN
4 RSTB
5 CGND
6 XIN
7 IGND
8 ICVDD
9 SCLK
10 SDATA
11 CSB
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
DALOUT
DAIN
IBS, TFS, IFS, LRIPOL,
IFORM, CKSEL, TEST
DAROUT
LROUT
BCKOUT
CGND
OVDD
NC
NC
NC
NC
NC
NC
1
LRIN 2
BCKIN 3
Input
Inter face
Bit Extension
ATT +
Deemphasis
DALOUT
BACS, BSO, OFORM,
LRPOL, DACS, TEST
24
DAROUT 23
LROUT 22
BCKOUT
RSTB
XIN
21
Output
Inter face
24
x2
1st FIR Filter
x2
2st FIR Filter
24
24
2fs
4fs
x2
3st FIR Filter
Soft Mute
8fs
IBS, BES, DIR
x8
Digital Filter
IFS, DFS, CKSE,
COES, ATT, DE
Note :
"n" in the Block diagram expresses the rate to sample
IFS, SMUTE,
TEST
LRCK
LRCK
LRCK
CKSE
4
6
Timing
Control
Syscllk
SDATA
CSB
10
SCLK 9
11
Microcomputer
Interface
n*
LRCK
n*
LRCK
n*
LRCK
24
24
24
No.
Name
I/O
Pin Function
1
DAIN
I
Audio data input
2
LRIN
I
L/R clock input
3
BCKIN
I
Bit clock input (48fs/64fs)
4
RSTB
I
System reset "0" = Reset
5
CGND
Ground (0V) for Core
System clock input (128fs/192fs/256fs/384fs/512fs/768fs)
Ground (0V) for Input Buffer
Power supply (3.3V) for Core and Input Buffer
Microcomputer interface clock input
Microcomputer interface data input
Microcomputer interface chip select input "0" = Enable, "1" = Disenable
16
NC
17
NC
18
OVDD
Power supply (3.3V) for Output Buffer
19
OGND
Ground (0V) for Output Buffer
20
CGND
Ground (0V) for Core
21
BCKOUT
O
Bit clock output (48fs/64fs)
22
LROUT
O
L/R clock output. WCLK output at PCM1704.
23
DAROUT
O
R ch audio data output
24
DALOUT
O
L ch audio data output or L/R ch multiplex output
IC807 : PD0274A
Audio Quality Enhancer (AQE)
Pin Arrangement
Block Diagram
Pin Function
ICs BLOCK DIAGRAM / TERMINAL DESCRIPTION
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