ON Semiconductor NCP1351B, Примечание к применению

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AND8344/D
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5
An NCP1351B controller was chosen for the standby
power supply. It is a current-mode pulse width modulation
(PWM) controller, which works with a variable frequency
and a quasi-fixed peak current. As the output load becomes
lighter, the operating frequency and peak current diminish.
This prevents mechanical resonance of the transformer and
limits acoustic noise. The low operating frequency also
increases efficiency by reducing switching losses.
The rectified voltage is brought to transformer TR2 and
switched by Q18. The NCP1351B drives the MOSFET
through resistor R114. Resistor R122 is placed only for
testing and evaluating of the gate drive signal. Resistors
R33, R110, R109 and capacitor C66 create a high-voltage
clamp that protect Q18 against high-voltage spikes
generated during MOSFET turn off by the leakage
inductance of the standby transformer. A parallel
combination of capacitors C70 and C71 sets a maximum
frequency beyond which no current flows into the FB.
A parallel combination of R129 and R130 forms a negative
current sense resistor, sensed through R131 and clamped by
C72. C73 becomes a timing capacitor if a current loop to FB
disappears. This capacitor is charged from an internal
current source, and, once this capacitor reaches 5 V, the IC
stops. D34 separates V
cc
during start-up conditions to
charge only that part necessary to start the standby power
supply. Once the standby starts working properly, it is
supplied from auxiliary winding W4 of the TR2 through
D29, which rectifies voltage from W4 and charges C55.
A start-up circuit is formed by D27, D28, R99, R100, R101
and R102, and the voltage for start-up is taken directly from
the ac mains. The values of resistors R99 to R101 are
selected to be small enough that capacitor C75 is charged in
a reasonable time for 120 Vac mains, yet large enough for
acceptable power dissipation given an input voltage of
265 Vac. Once capacitor C75 is charged to the level
necessary to turn on the NCP1351B, the SMPS is powered
from auxiliary winding W4 of the TR2. The circuit around
Q17, R108, R113, R116, R127, and R128 is used to turn off
the standby SMPS if the mains input is disconnected
(e.g. main switch is turned off). If the mains voltage is at
high line and the output consumption is very low,
discharging the bulk through a small load takes a very long
time and it is possible that an indicator LED would remain
on too long and it would be difficult to determine whether the
LCD TV is turned off or not. So, if the mains disappears, the
voltage at the base of Q17 disappears as well. This means
that Q17 turns off, the LATCH pin of the NCP1351B is
pulled up through R108 and R116, and the output pulses
stop. In case of a quick restoration of the mains or a brief
transient drop, the voltage from LATCH is brought to base
Q20 through R120. If the latch is pulled up, Q20 shorts the
V
cc
line and resets the internal latch logic inside the
NCP1351B.
NOTE: The circuit coupling around Q17 and Q20 is not mandatory
for proper function of SMPS. This is provided to illustrate
how to address this functionality if it is required.
The Secondary Side:
Figure 5. The SMPS Secondary Side Schematic
Voltage from the transformer is rectified by diode D30 and
filtered by the set of capacitors C58, C59, C60, C61, C62 and
inductor L13. Part of this voltage is available for powering
the control circuit and the remainder is switched by Q15 to
the 5 V output when the main SMPS is activated and an
output voltage of 12 V is presented. The level of the output
voltage is set by resistor divider R125 and R136. The bias
current for TL431B is set by resistor R124. Stability and
speed of response for transients are set by resistor R121 and
capacitors C76 and C79 on the secondary side. For the
choice of appropriate devices and for setting the appropriate
loop gain and phase margin, please see application note
AND8327/D . The gain margin achieved with the devices
used here is shown in Figure 6.
Gain chart
−30
−20
−10
0
10
20
30
0.1 0.2 0.3 0.5 0.8 1.3 2.1 3.5 5.8 9.6 16
Frequency [kHz]
Gain [dB]
−180
−120
−60
0
60
120
180
Phase
[
°
]
Figure 6. Frequency Response of the Open
Regulation Loop of the STBY
Gain
Phase